[PATCH v3 0/6] spi: microchip-core: Code improvements

[PATCH v3 0/6] spi: microchip-core: Code improvements

[Andy Shevchenko]

While reading some other stuff, I noticed that this driver may
be improved. Here is the set of refactoring and cleaning it up.

Changelog v3:
- collected tags (Prajna)
- restored dummy read in TX-only transfers

v2: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com>

Changelog v2:
- dropped device property agnostic API conversion change (Mark)

Andy Shevchenko (6):
  spi: microchip-core: use min() instead of min_t()
  spi: microchip-core: Refactor FIFO read and write handlers
  spi: microchip-core: Replace dead code (-ENOMEM error message)
  spi: microchip-core: Utilise temporary variable for struct device
  spi: microchip-core: Use SPI_MODE_X_MASK
  spi: microchip-core: Remove unneeded PM related macro

 drivers/spi/spi-microchip-core-spi.c | 95 ++++++++++++----------------
 1 file changed, 40 insertions(+), 55 deletions(-)

-- 
2.50.1

[PATCH v3 1/6] spi: microchip-core: use min() instead of min_t()

[Andy Shevchenko]

min_t(int, a, b) casts an 'unsigned int' to 'int'. This might lead
to the cases when big number is wrongly chosen. On the other hand,
the SPI transfer length is unsigned and driver uses signed type for
an unknown reason. Change the type of the transfer length to be
unsigned and convert use min() instead of min_t().

Reviewed-by: David Laight <david.laight.linux@gmail.com>
Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index 16e0885474a0..08ccdc5f0cc9 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -74,8 +74,8 @@ struct mchp_corespi {
 	u8 *rx_buf;
 	u32 clk_gen;
 	int irq;
-	int tx_len;
-	int rx_len;
+	unsigned int tx_len;
+	unsigned int rx_len;
 	u32 fifo_depth;
 };
 
@@ -214,7 +214,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
 		       spi->regs + MCHP_CORESPI_REG_INTCLEAR);
 		finalise = true;
 		dev_err(&host->dev,
-			"RX OVERFLOW: rxlen: %d, txlen: %d\n",
+			"RX OVERFLOW: rxlen: %u, txlen: %u\n",
 			spi->rx_len, spi->tx_len);
 	}
 
@@ -223,7 +223,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
 		       spi->regs + MCHP_CORESPI_REG_INTCLEAR);
 		finalise = true;
 		dev_err(&host->dev,
-			"TX UNDERFLOW: rxlen: %d, txlen: %d\n",
+			"TX UNDERFLOW: rxlen: %u, txlen: %u\n",
 			spi->rx_len, spi->tx_len);
 	}
 
@@ -283,7 +283,7 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
 	spi->rx_len = xfer->len;
 
 	while (spi->tx_len) {
-		int fifo_max = min_t(int, spi->tx_len, spi->fifo_depth);
+		unsigned int fifo_max = min(spi->tx_len, spi->fifo_depth);
 
 		mchp_corespi_write_fifo(spi, fifo_max);
 		mchp_corespi_read_fifo(spi, fifo_max);
-- 
2.50.1

[PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers

[Andy Shevchenko]

Make both handlers to be shorter and easier to understand.
While at it, unify their style.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 31 +++++++++++-----------------
 1 file changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index 08ccdc5f0cc9..439745a36f9c 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -97,15 +97,12 @@ static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi, u32 fifo_max
 		       MCHP_CORESPI_STATUS_RXFIFO_EMPTY)
 			;
 
+		/* On TX-only transfers always perform a dummy read */
 		data = readb(spi->regs + MCHP_CORESPI_REG_RXDATA);
+		if (spi->rx_buf)
+			*spi->rx_buf++ = data;
 
 		spi->rx_len--;
-		if (!spi->rx_buf)
-			continue;
-
-		*spi->rx_buf = data;
-
-		spi->rx_buf++;
 	}
 }
 
@@ -127,23 +124,19 @@ static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
 
 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32 fifo_max)
 {
-	int i = 0;
-
-	while ((i < fifo_max) &&
-	       !(readb(spi->regs + MCHP_CORESPI_REG_STAT) &
-		 MCHP_CORESPI_STATUS_TXFIFO_FULL)) {
-		u32 word;
-
-		word = spi->tx_buf ? *spi->tx_buf : 0xaa;
-		writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA);
+	for (int i = 0; i < fifo_max; i++) {
+		if (readb(spi->regs + MCHP_CORESPI_REG_STAT) &
+		    MCHP_CORESPI_STATUS_TXFIFO_FULL)
+			break;
 
+		/* On RX-only transfers always perform a dummy write */
 		if (spi->tx_buf)
-			spi->tx_buf++;
+			writeb(*spi->tx_buf++, spi->regs + MCHP_CORESPI_REG_TXDATA);
+		else
+			writeb(0xaa, spi->regs + MCHP_CORESPI_REG_TXDATA);
 
-		i++;
+		spi->tx_len--;
 	}
-
-	spi->tx_len -= i;
 }
 
 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
-- 
2.50.1

RE: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers

[Prajna.Rajendrakumar]

> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: Thursday, November 27, 2025 6:59 PM
> To: Prajna Rajendra kumar - M74368
> <Prajna.Rajendrakumar@microchip.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; linux-spi@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Cc: Mark Brown <broonie@kernel.org>
> Subject: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write
> handlers
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
> 
> Make both handlers to be shorter and easier to understand.
> While at it, unify their style.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
> ---
>  drivers/spi/spi-microchip-core-spi.c | 31 +++++++++++-----------------
>  1 file changed, 12 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-
> core-spi.c
> index 08ccdc5f0cc9..439745a36f9c 100644
> --- a/drivers/spi/spi-microchip-core-spi.c
> +++ b/drivers/spi/spi-microchip-core-spi.c
> @@ -97,15 +97,12 @@ static inline void mchp_corespi_read_fifo(struct
> mchp_corespi *spi, u32 fifo_max
>                        MCHP_CORESPI_STATUS_RXFIFO_EMPTY)
>                         ;
> 
> +               /* On TX-only transfers always perform a dummy read */
>                 data = readb(spi->regs + MCHP_CORESPI_REG_RXDATA);
> +               if (spi->rx_buf)
> +                       *spi->rx_buf++ = data;
> 
>                 spi->rx_len--;
> -               if (!spi->rx_buf)
> -                       continue;
> -
> -               *spi->rx_buf = data;
> -
> -               spi->rx_buf++;
>         }
>  }
> 
> @@ -127,23 +124,19 @@ static void mchp_corespi_disable_ints(struct
> mchp_corespi *spi)
> 
>  static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi, u32
> fifo_max)  {
> -       int i = 0;
> -
> -       while ((i < fifo_max) &&
> -              !(readb(spi->regs + MCHP_CORESPI_REG_STAT) &
> -                MCHP_CORESPI_STATUS_TXFIFO_FULL)) {
> -               u32 word;
> -
> -               word = spi->tx_buf ? *spi->tx_buf : 0xaa;
> -               writeb(word, spi->regs + MCHP_CORESPI_REG_TXDATA);
> +       for (int i = 0; i < fifo_max; i++) {
> +               if (readb(spi->regs + MCHP_CORESPI_REG_STAT) &
> +                   MCHP_CORESPI_STATUS_TXFIFO_FULL)
> +                       break;
> 
> +               /* On RX-only transfers always perform a dummy write */
>                 if (spi->tx_buf)
> -                       spi->tx_buf++;
> +                       writeb(*spi->tx_buf++, spi->regs +
> MCHP_CORESPI_REG_TXDATA);
> +               else
> +                       writeb(0xaa, spi->regs +
> + MCHP_CORESPI_REG_TXDATA);
> 
> -               i++;
> +               spi->tx_len--;
>         }
> -
> -       spi->tx_len -= i;
>  }
> 
>  static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
> --
> 2.50.1

Re: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers

[Andy Shevchenko]

On Fri, Nov 28, 2025 at 02:16:27PM +0000, Prajna.Rajendrakumar@microchip.com wrote:
> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Sent: Thursday, November 27, 2025 6:59 PM

> > Make both handlers to be shorter and easier to understand.
> > While at it, unify their style.
> > 
> Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>

Thanks, I assume now it works? Since Mark applied all but this patch from v3,
I am going to submit it separately with your tag included.

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write handlers

[Prajna.Rajendrakumar]

> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: Friday, November 28, 2025 3:40 PM
> To: Prajna Rajendra kumar - M74368
> <Prajna.Rajendrakumar@microchip.com>
> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org;
> broonie@kernel.org; Conor Dooley - M52691
> <Conor.Dooley@microchip.com>
> Subject: Re: [PATCH v3 2/6] spi: microchip-core: Refactor FIFO read and write
> handlers
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
> 
> On Fri, Nov 28, 2025 at 02:16:27PM +0000,
> Prajna.Rajendrakumar@microchip.com wrote:
> > > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > > Sent: Thursday, November 27, 2025 6:59 PM
> 
> > > Make both handlers to be shorter and easier to understand.
> > > While at it, unify their style.
> > >
> > Reviewed-by: Prajna Rajendra Kumar
> > <prajna.rajendrakumar@microchip.com>
> 
> Thanks, I assume now it works? Since Mark applied all but this patch from v3,
> I am going to submit it separately with your tag included.
> 
> --
> With Best Regards,
> Andy Shevchenko
> 
Yes, works as expected. Thanks for pushing this separately.

Best regards,
Prajna

[PATCH v3 3/6] spi: microchip-core: Replace dead code (-ENOMEM error message)

[Andy Shevchenko]

First of all, the convention in the kernel that we do not issue
error messages for -ENOMEM. Second, it's ignored by dev_err_probe().
Replace dead code by a simple return statement.

Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index 439745a36f9c..fa6fb2d3f7d0 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -298,8 +298,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 
 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
 	if (!host)
-		return dev_err_probe(&pdev->dev, -ENOMEM,
-				     "unable to allocate host for SPI controller\n");
+		return -ENOMEM;
 
 	platform_set_drvdata(pdev, host);
 
-- 
2.50.1

[PATCH v3 4/6] spi: microchip-core: Utilise temporary variable for struct device

[Andy Shevchenko]

Add a temporary variable to keep a pointer to struct device.
Utilise it where it makes sense.

Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 44 +++++++++++++---------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index fa6fb2d3f7d0..0ece51460ee0 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -289,6 +289,7 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
 static int mchp_corespi_probe(struct platform_device *pdev)
 {
 	const char *protocol = "motorola";
+	struct device *dev = &pdev->dev;
 	struct spi_controller *host;
 	struct mchp_corespi *spi;
 	struct resource *res;
@@ -296,13 +297,13 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	bool assert_ssel;
 	int ret = 0;
 
-	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
+	host = devm_spi_alloc_host(dev, sizeof(*spi));
 	if (!host)
 		return -ENOMEM;
 
 	platform_set_drvdata(pdev, host);
 
-	if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
+	if (of_property_read_u32(dev->of_node, "num-cs", &num_cs))
 		num_cs = MCHP_CORESPI_MAX_CS;
 
 	/*
@@ -310,12 +311,12 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	 * CoreSPI can be configured for Motorola, TI or NSC.
 	 * The current driver supports only Motorola mode.
 	 */
-	ret = of_property_read_string(pdev->dev.of_node, "microchip,protocol-configuration",
+	ret = of_property_read_string(dev->of_node, "microchip,protocol-configuration",
 				      &protocol);
 	if (ret && ret != -EINVAL)
-		return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configuration\n");
+		return dev_err_probe(dev, ret, "Error reading protocol-configuration\n");
 	if (strcmp(protocol, "motorola") != 0)
-		return dev_err_probe(&pdev->dev, -EINVAL,
+		return dev_err_probe(dev, -EINVAL,
 				     "CoreSPI: protocol '%s' not supported by this driver\n",
 				      protocol);
 
@@ -323,11 +324,11 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	 * Motorola mode (0-3): CFG_MOT_MODE
 	 * Mode is fixed in the IP configurator.
 	 */
-	ret = of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode", &mode);
+	ret = of_property_read_u32(dev->of_node, "microchip,motorola-mode", &mode);
 	if (ret)
 		mode = MCHP_CORESPI_DEFAULT_MOTOROLA_MODE;
 	else if (mode > 3)
-		return dev_err_probe(&pdev->dev, -EINVAL,
+		return dev_err_probe(dev, -EINVAL,
 				     "invalid 'microchip,motorola-mode' value %u\n", mode);
 
 	/*
@@ -335,9 +336,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	 * The hardware allows frame sizes <= APB data width.
 	 * However, this driver currently only supports 8-bit frames.
 	 */
-	ret = of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &frame_size);
+	ret = of_property_read_u32(dev->of_node, "microchip,frame-size", &frame_size);
 	if (!ret && frame_size != 8)
-		return dev_err_probe(&pdev->dev, -EINVAL,
+		return dev_err_probe(dev, -EINVAL,
 				     "CoreSPI: frame size %u not supported by this driver\n",
 				     frame_size);
 
@@ -347,9 +348,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	 * To prevent CS deassertion when TX FIFO drains, the ssel-active property
 	 * keeps CS asserted for the full SPI transfer.
 	 */
-	assert_ssel = of_property_read_bool(pdev->dev.of_node, "microchip,ssel-active");
+	assert_ssel = of_property_read_bool(dev->of_node, "microchip,ssel-active");
 	if (!assert_ssel)
-		return dev_err_probe(&pdev->dev, -EINVAL,
+		return dev_err_probe(dev, -EINVAL,
 				     "hardware must enable 'microchip,ssel-active' to keep CS asserted for the SPI transfer\n");
 
 	spi = spi_controller_get_devdata(host);
@@ -361,9 +362,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 	host->transfer_one = mchp_corespi_transfer_one;
 	host->set_cs = mchp_corespi_set_cs;
-	host->dev.of_node = pdev->dev.of_node;
+	host->dev.of_node = dev->of_node;
 
-	ret = of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_depth);
+	ret = of_property_read_u32(dev->of_node, "fifo-depth", &spi->fifo_depth);
 	if (ret)
 		spi->fifo_depth = MCHP_CORESPI_DEFAULT_FIFO_DEPTH;
 
@@ -375,24 +376,21 @@ static int mchp_corespi_probe(struct platform_device *pdev)
 	if (spi->irq < 0)
 		return spi->irq;
 
-	ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
-			       IRQF_SHARED, dev_name(&pdev->dev), host);
+	ret = devm_request_irq(dev, spi->irq, mchp_corespi_interrupt, IRQF_SHARED,
+			       dev_name(dev), host);
 	if (ret)
-		return dev_err_probe(&pdev->dev, ret,
-				     "could not request irq\n");
+		return dev_err_probe(dev, ret, "could not request irq\n");
 
-	spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+	spi->clk = devm_clk_get_enabled(dev, NULL);
 	if (IS_ERR(spi->clk))
-		return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
-				     "could not get clk\n");
+		return dev_err_probe(dev, PTR_ERR(spi->clk), "could not get clk\n");
 
 	mchp_corespi_init(host, spi);
 
-	ret = devm_spi_register_controller(&pdev->dev, host);
+	ret = devm_spi_register_controller(dev, host);
 	if (ret) {
 		mchp_corespi_disable(spi);
-		return dev_err_probe(&pdev->dev, ret,
-				     "unable to register host for CoreSPI controller\n");
+		return dev_err_probe(dev, ret, "unable to register host for CoreSPI controller\n");
 	}
 
 	return 0;
-- 
2.50.1

[PATCH v3 5/6] spi: microchip-core: Use SPI_MODE_X_MASK

[Andy Shevchenko]

Use SPI_MODE_X_MASK instead of open coded variant.

Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index 0ece51460ee0..d37e193e282f 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -153,8 +153,6 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
 
 static int mchp_corespi_setup(struct spi_device *spi)
 {
-	u32 dev_mode = spi->mode & (SPI_CPOL | SPI_CPHA);
-
 	if (spi_get_csgpiod(spi, 0))
 		return 0;
 
@@ -163,7 +161,7 @@ static int mchp_corespi_setup(struct spi_device *spi)
 		return -EOPNOTSUPP;
 	}
 
-	if (dev_mode & ~spi->controller->mode_bits) {
+	if ((spi->mode ^ spi->controller->mode_bits) & SPI_MODE_X_MASK) {
 		dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Motorola mode\n");
 		return -EINVAL;
 	}
-- 
2.50.1

[PATCH v3 6/6] spi: microchip-core: Remove unneeded PM related macro

[Andy Shevchenko]

Static declaration by default are 0 or NULL, no need to initialise
them explicitly. Remove unneeded PM related macro.

Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/spi/spi-microchip-core-spi.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
index d37e193e282f..2f4b21ad56a7 100644
--- a/drivers/spi/spi-microchip-core-spi.c
+++ b/drivers/spi/spi-microchip-core-spi.c
@@ -403,8 +403,6 @@ static void mchp_corespi_remove(struct platform_device *pdev)
 	mchp_corespi_disable(spi);
 }
 
-#define MICROCHIP_SPI_PM_OPS (NULL)
-
 /*
  * Platform driver data structure
  */
@@ -421,7 +419,6 @@ static struct platform_driver mchp_corespi_driver = {
 	.probe = mchp_corespi_probe,
 	.driver = {
 		.name = "microchip-corespi",
-		.pm = MICROCHIP_SPI_PM_OPS,
 		.of_match_table = of_match_ptr(mchp_corespi_dt_ids),
 	},
 	.remove = mchp_corespi_remove,
-- 
2.50.1

Re: [PATCH v3 0/6] spi: microchip-core: Code improvements

[Mark Brown]

On Thu, 27 Nov 2025 19:58:57 +0100, Andy Shevchenko wrote:
> While reading some other stuff, I noticed that this driver may
> be improved. Here is the set of refactoring and cleaning it up.
> 
> Changelog v3:
> - collected tags (Prajna)
> - restored dummy read in TX-only transfers
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/6] spi: microchip-core: use min() instead of min_t()
      commit: e29aca7038f3c292c18048922c5f4436a034da99
[2/6] spi: microchip-core: Refactor FIFO read and write handlers
      (no commit info)
[3/6] spi: microchip-core: Replace dead code (-ENOMEM error message)
      commit: 274b3458af1f9c665faae70b560852461c30acef
[4/6] spi: microchip-core: Utilise temporary variable for struct device
      commit: 06b010d3c778075108041074a8fb785074231ac4
[5/6] spi: microchip-core: Use SPI_MODE_X_MASK
      commit: 4db5a0705b1e03abb6ff4e7d7789b32c31384429
[6/6] spi: microchip-core: Remove unneeded PM related macro
      commit: f458fc9b1946bc882a217d65bfe5ba50787f253f

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark