[PATCH V2 1/3] dt-bindings: spi: Add support for ATCSPI200 SPI controller

[CL Wang <cl634@andestech.com>]

Document devicetree bindings for the Andes ATCSPI200 SPI controller.

Signed-off-by: CL Wang <cl634@andestech.com>
  - Dropped the "spi_" prefix from dma-names as suggested.
  - Updated the DT binding and documented all compatible strings.
  - Added the "andestech,ae350-spi" compatible string.
    
    AE350 is part of the AndeShape™ platform family and is a commercially
    supported product with a fixed, documented SoC-level architecture (memory
    map, interrupt topology, and peripheral integration). Although AE350 is
    often deployed on FPGA boards, the platform behaves as a stable SoC
    integration rather than a prototype.
    
    Upstream Linux already accepts FPGA-based platform-level compatible strings
    for stable SoC-like integrations. For example, the Tensilica FPGA platform
    uses:
    compatible = "cdns,xtfpga-spi";
   
    Following the same rationale, "andestech,ae350-spi" is proposed as the
    platform-level compatible string for AE350-based devices.

    More information about AE350 can be found at:
    https://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/

---
 .../bindings/spi/andestech,qilai-spi.yaml     | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/andestech,qilai-spi.yaml

diff --git a/Documentation/devicetree/bindings/spi/andestech,qilai-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,qilai-spi.yaml
new file mode 100644
index 000000000000..e58e6d675d70
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/andestech,qilai-spi.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/andestech,qilai-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes ATCSPI200 SPI controller
+
+maintainers:
+  - CL Wang <cl634@andestech.com>
+
+properties:
+  compatible:
+    enum:
+      - andestech,qilai-spi
+      - andestech,ae350-spi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  num-cs:
+    description: Number of chip selects supported
+    maxItems: 1
+
+  dmas:
+    items:
+      - description: Transmit FIFO DMA channel
+      - description: Receive FIFO DMA channel
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+patternProperties:
+  "@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      spi-rx-bus-width:
+        enum: [1, 4]
+
+      spi-tx-bus-width:
+        enum: [1, 4]
+
+allOf:
+  - $ref: spi-controller.yaml#
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - dmas
+  - dma-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      spi@f0b00000 {
+        compatible = "andestech,qilai-spi";
+        reg = <0x0 0xf0b00000 0x0 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clocks = <&clk_spi>;
+        dmas = <&dma0 0>, <&dma0 1>;
+        dma-names = "tx", "rx";
+
+        flash@0 {
+          compatible = "jedec,spi-nor";
+          reg = <0x0>;
+          spi-tx-bus-width = <0x4>;
+          spi-rx-bus-width = <0x4>;
+          spi-cpol;
+          spi-cpha;
+        };
+      };
+    };
-- 
2.34.1