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Tue, 19 May 2026 08:51:10 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Laxman Dewangan , Sowjanya Komatineni , Breno Leitao , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH v2 2/3] spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler Date: Tue, 19 May 2026 15:51:07 +0000 Message-ID: <20260519155108.4092518-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260519155108.4092518-1-va@nvidia.com> References: <20260519155108.4092518-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C8:EE_|DS0PR12MB7777:EE_ X-MS-Office365-Filtering-Correlation-Id: d03eac72-ac64-47d8-c500-08deb5be8133 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|56012099003|22082099003|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WGrqEvjTKo4W7e1q9Re50R9nb2RI8jB1ZTG6sjg26XLqUBBhJxlD59IRY6wd7OYzpN7XPhcqKOmoVzHbRBd4LdgDf7ukEqt9YusEUDbbe/80iqvpNFcNeDyKPW5H6jEDykbsZOyPg/akczWTwkd/WNNRKqJnUkvocD1PRIM/iHaPvee9CCbeQmx/E4hiSs9e7o9wH5FDf7sdSgDkoPq50HxjT93EuFWVRDbRK609fjeACz4xC0GmdK/pDZ6Arx2Cn7I8fNcT6bsqTSnEGXcG8VP2GHozeCCl8nfwg7Nw6/wXmy1wtoDO0sejySWisvsF+co5bNm0qRCHhafhpUzIeClZCNG08ZZzAuOts1v6/+yTKqshsTO+bO8L2Nl7FwkProGJXMsNOnd9lyHJTsDrCKDgsBIYnVx3IBPVBj3UEEXLqkhEXCXFyUjwav2HZQr6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 15:51:34.7856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d03eac72-ac64-47d8-c500-08deb5be8133 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7777 The threaded IRQ handler reads QSPI_TRANS_STATUS to check for transfer completion, but on heavily loaded systems, the thread can be delayed long enough for wait_for_completion_timeout() to expire first. When the timeout handler then reads TRANS_STATUS directly from hardware, it may see a completed transfer but race with the (now-running) IRQ thread, leading to double completion or use-after-free on curr_xfer. With the conversion to hard IRQ + workqueue in the previous patch, this race still exists: the workqueue bottom-half can be delayed past the timeout, and the timeout handler reading hardware directly has no synchronization with the ISR's cached state. Cache QSPI_TRANS_STATUS in the ISR before clearing it, allowing the timeout handler to check the cached value under spinlock. Also guard against curr_xfer being NULLed by a concurrent workqueue completion. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 17d0b511af1d..72f66f2c6dab 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -214,6 +214,7 @@ struct tegra_qspi { u32 tx_status; u32 rx_status; u32 status_reg; + u32 trans_status; bool is_packed; bool use_dma; @@ -854,6 +855,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran tqspi->cur_rx_pos = 0; tqspi->cur_tx_pos = 0; tqspi->curr_xfer = t; + tqspi->trans_status = 0; spin_unlock_irqrestore(&tqspi->lock, flags); if (is_first_of_msg) { @@ -1068,26 +1070,30 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi); */ static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) { + unsigned long flags; irqreturn_t ret; - u32 status; - /* Check if hardware actually completed the transfer */ - status = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - if (!(status & QSPI_RDY)) + spin_lock_irqsave(&tqspi->lock, flags); + + if (!(tqspi->trans_status & QSPI_RDY)) { + spin_unlock_irqrestore(&tqspi->lock, flags); return -ETIMEDOUT; + } /* - * Hardware completed but interrupt was lost/delayed. Manually - * process the completion by calling the appropriate handler. + * ISR or workqueue may have already completed the transfer + * and NULLed curr_xfer between the completion timeout and now. */ + if (!tqspi->curr_xfer) { + spin_unlock_irqrestore(&tqspi->lock, flags); + return 0; + } + + spin_unlock_irqrestore(&tqspi->lock, flags); + dev_warn_ratelimited(tqspi->dev, "QSPI interrupt timeout, but transfer complete\n"); - /* Clear the transfer status */ - status = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); - - /* Manually trigger completion handler */ if (!tqspi->is_curr_dma_xfer) ret = handle_cpu_based_xfer(tqspi); else @@ -1642,6 +1648,8 @@ static irqreturn_t tegra_qspi_isr(int irq, void *context_data) if (!(status & QSPI_RDY)) return IRQ_NONE; + tqspi->trans_status = status; + spin_lock(&tqspi->lock); tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); tegra_qspi_mask_clear_irq(tqspi); -- 2.17.1