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Tue, 19 May 2026 08:51:11 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Laxman Dewangan , Sowjanya Komatineni , Breno Leitao , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH v2 3/3] spi: tegra210-quad: Process small PIO transfers in hard IRQ context Date: Tue, 19 May 2026 15:51:08 +0000 Message-ID: <20260519155108.4092518-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260519155108.4092518-1-va@nvidia.com> References: <20260519155108.4092518-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CC:EE_|DS7PR12MB6191:EE_ X-MS-Office365-Filtering-Correlation-Id: 83e935d4-5ebe-4a8a-ce7b-08deb5be816f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|56012099003|18002099003|22082099003|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wHXhc0GDbhz8txWY/8oXb3bgXe014OLfwlL1RIT3lOsHG0V8eVYMP64fd7ytBZ5adTHY/7ZEaajUqCFYx3aQYlPoP/lSlEJsVbfB8buc1E2tzg3dPlTdzdIRA5ijECIhdwBktRYNu1KremlS8ofttM0PB1DHv6pdjQBAHsNwzCg6sy8E44UQ1S+rtonsGRwUfzQ+rKA44svcjpaCM74dBMHc4HlO6hQH0olSIY+x+zjuo0zc8QBNZv53iCbNOHr6J+lk0f/yakRFDowT451QNLVK+NjRLNZVbwS1CJWz4zxKxdJ7PhooNrIgeyBDLgLqfa351rWmm0yjRAEPmq0KVlSxwsEVX/f8xRcVW+tbsuCNqySkcb8YPFDOUPDn65PM1Hoe5lIGy4mp5CKdT76+2wLoARBHnJxqYlsFfHR420kb/dASlfpiUAU1k1CnRzxc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 15:51:35.1787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83e935d4-5ebe-4a8a-ce7b-08deb5be816f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6191 On heavily loaded systems, workqueue scheduling delays can exceed transfer timeouts even for high-priority queues, causing false timeouts for latency-sensitive devices like TPM despite hardware completing in microseconds. Process small PIO transfers (≤256 bytes) directly in hard IRQ context instead of deferring to workqueue. This reduces completion latency from 1000ms+ to microseconds and matches the pattern used by other SPI drivers. The 256-byte threshold (FIFO depth) ensures small transfers for devices like TPMs use the fast path, while larger transfers continue using workqueue. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 72f66f2c6dab..bb3c51b3a57d 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1664,6 +1664,15 @@ static irqreturn_t tegra_qspi_isr(int irq, void *context_data) spin_unlock(&tqspi->lock); + /* + * For small PIO transfers (e.g., TPM), process directly in hard IRQ + * context unless there was a FIFO error. Error recovery calls + * device_reset() which can sleep, so must be deferred to workqueue. + */ + if (!tqspi->is_curr_dma_xfer && tqspi->curr_dma_words <= QSPI_FIFO_DEPTH && + !tqspi->tx_status && !tqspi->rx_status) + return handle_cpu_based_xfer(tqspi); + queue_work(tqspi->wq, &tqspi->irq_work); return IRQ_HANDLED; -- 2.17.1