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Fri, 22 May 2026 02:09:17 -0700 From: Vishwaroop A To: Breno Leitao CC: Vishwaroop A , Thierry Reding , Jonathan Hunter , Mark Brown , Laxman Dewangan , Sowjanya Komatineni , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: Re: [PATCH v2 1/3] spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue Date: Fri, 22 May 2026 09:09:17 +0000 Message-ID: <20260522090917.220650-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: <20260519155108.4092518-1-va@nvidia.com> <20260519155108.4092518-2-va@nvidia.com> <20260520192210.70216-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CB:EE_|MN2PR12MB4253:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f166e21-bfd5-4761-5d22-08deb7e1d759 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|11063799006|4143699003|6133799003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: m5huMNOPJTRXO+QrGoC9WYefd4mmBzAD9CBwnJLOQ63vrWso8Gh1AQJGEoYP1X8lIhqzV1HGfwPnqCYn90Ada4cjMK+DMuO5z1la97HB9BKIzMmn47Yfnl9catCaNJ7km1ZOFpNXjF8yNOBDZpdVAIaLhdkz3LvLuymPbFRFOD0qAl0A3HQnR85925/wWxbsFwr1BpYA9bZPeODuna03/jeMuS7RcYGy0DCFxw49R/9AGeGtcobaLlvRyr8EciA97rJ9ct4MO5r5k8Tq44APO/l7LoOsHlJwqhzOMuFDyd14iVnMN4X7mCHREfzgTlzYR1E7BShkBw2pEbcX2YdZtRtgg1qNMCsMjg7eji422vcxoTN/6Nu0r3C13TaFPQmrxPjE1m0JifCNh31CJ5mBoFm0BYkYw+cnMRZRQwK6UT6Sbmfx9xjpmWR8EMDFfn3/dCs2yqq5V+rYdZbUsnX1WKVR7gyu5fEPY0p99YiQf3XtEHoZofN6k6r6UhkQfmJfhAVwTjEMvNoNn4KpULmXqT1TY7DFMuAvG0uS+Z7bm3OoZVXWNgVz/NFMYS9TQvxyDjz6sFOsNrSDwi2zi+rwRhRLpG3bamh80jYEIb0sSrs2hX3MixcPKT4IKzQ5l9yaPDdoLRiGu4lwtiRl8mEj0esusn8bcqkUPXEQSyRIdFZzHVLvks91nEekPShtlNCEEsjsZpsBYwl+UHPL9c5DYLf3zEwXOlhsw6qRzdJc3UI= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(11063799006)(4143699003)(6133799003)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: H13L/DXlWcTspNNt3ee/rrtyens/6TG0RuUc48hD89WD/YjxhQINGoBe8Nd498Q57mpwNoTA2qNZ8C/3NDr+HHF0uYgobbCRiX2PRGf8oycM0KAADSGUf27sKpbAyU1Bf/ClsLlFupNPxVQ4jtlIBFqZAEFuPvHSKk1EoS4NaImEZU60Au8O5eS+lJ7Smf0DSNR3yks9kBxLaQpEeJyElHjACsGGOnrmwP8p+65a46p3rqGnkmQa2bCvBrH4CCpI6kVgib0KtQP+MRBbA0rCHtx7YMt09zlMGHLNeIks7Fa75ZVQ9IFEZB1C1SKdhCwLsIRxj+uN2cOxTfIbPL60fp5goXhULs7OXeH/9eSF02dnFxo7Ziq1f3f7ze7yzTDyL9mmEj+vEZJ6tL8WQ8q3dmus6SffQJ/4aKhSBuWxzX5BNtfcphTtsiemhwpc5xec X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2026 09:09:34.1067 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f166e21-bfd5-4761-5d22-08deb7e1d759 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4253 On Thu, May 21, 2026 at 08:04:08AM -0700, Breno Leitao wrote: > If the lock is really only guarding curr_xfer / status_reg / tx_status > / rx_status, why hold it across those register accesses at all? Thanks for pushing on this, it's a fair question and worth spelling out more carefully. The lock spans the register accesses because the FIFO_STATUS read and the tx_status / rx_status / status_reg writes form one update -- the software fields are populated directly from that read. The bottom-half (handle_cpu_based_xfer at line 1467) and the timeout handler (which calls into handle_cpu_based_xfer at line 1098 after releasing its own acquisition at line 1092) both read tx_status and rx_status under the same lock. Splitting the lock so the read is outside would let those callers observe partially updated software state. The mask_clear_irq call is inside the same critical section because it is the W1C that retires the interrupt source the ISR just consumed. Pairing it with the FIFO_STATUS read and the software writes ensures that any subsequent acquirer of the lock sees either "interrupt is pending and software fields are stale" or "interrupt is retired and software fields are current" -- never the middle state. handle_cpu_based_xfer holds the lock across its FIFO drain and sub-transfer restart for the same reason: the restart calls tegra_qspi_unmask_irq, which can re-trigger the ISR before the handler finishes setting curr_xfer = NULL at line 1497. Releasing the lock only after that assignment lets the next ISR's critical section start from a consistent state. TRANS_STATUS is read outside the lock because that read precedes the sequence -- it is the IRQF_SHARED ownership check, a single readl with no associated software state and no RMW. The two CPU-side paths that clear it are tegra_qspi_mask_clear_irq inside the ISR's locked section (line 1655) and tegra_qspi_mask_clear_irq from setup_transfer_one (line 862), which runs before the controller unmasks its interrupts, so it cannot overlap with an ISR. Vishwaroop