From: Krzysztof Kozlowski <krzk@kernel.org>
To: Chi-Wen Weng <cwweng.linux@gmail.com>
Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, cwweng@nuvoton.com
Subject: Re: [PATCH v2 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI
Date: Mon, 8 Jun 2026 12:02:44 +0200 [thread overview]
Message-ID: <20260608-aquatic-alluring-asp-b5fcb6@quoll> (raw)
In-Reply-To: <20260608025009.1504971-2-cwweng@nuvoton.com>
On Mon, Jun 08, 2026 at 10:50:08AM +0800, Chi-Wen Weng wrote:
> Add a devicetree binding for the Quad SPI controller found in
> Nuvoton MA35D1 SoCs.
>
> The controller supports SPI memory devices such as SPI NOR and SPI NAND
> flashes. It has one register range, one clock input and one reset line,
> and supports up to two chip selects.
>
> Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com>
DCO mismatch.
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-06-08 10:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-08 2:50 [PATCH v2 0/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller Chi-Wen Weng
2026-06-08 2:50 ` [PATCH v2 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI Chi-Wen Weng
2026-06-08 10:02 ` Krzysztof Kozlowski [this message]
2026-06-08 11:41 ` Chi-Wen Weng
2026-06-08 2:50 ` [PATCH v2 2/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller support Chi-Wen Weng
2026-06-08 10:53 ` Mark Brown
2026-06-08 11:45 ` Chi-Wen Weng
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