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Thu, 9 Jul 2026 05:52:23 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Sudip Mukherjee , Serge Semin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Changhuang Liang Subject: [PATCH v1 07/11] spi: dw: use irq handler for enhanced spi Date: Wed, 8 Jul 2026 22:52:00 -0700 Message-Id: <20260709055204.138168-8-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260709055204.138168-1-changhuang.liang@starfivetech.com> References: <20260709055204.138168-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0024.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::8) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1282:EE_ X-MS-Office365-Filtering-Correlation-Id: d73cc285-388f-41d8-0671-08dedd7e3f69 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|23010399003|376014|366016|38350700014|5023799004|56012099006|22082099003|18002099003; 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Also, use the xfer_completion from spi_controller to wait for a timeout or completion from irq handler. In enhanced mode we need to calculate RXFTLR based on the length of data we are expecting to receive or the fifo length. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 93 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 9f0f7e0b93a1..532441da235e 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -248,6 +248,34 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws) return IRQ_HANDLED; } +static irqreturn_t dw_spi_enh_handler(struct dw_spi *dws) +{ + u16 irq_status = dw_readl(dws, DW_SPI_ISR); + + if (dw_spi_check_status(dws, false)) { + spi_finalize_current_transfer(dws->ctlr); + return IRQ_HANDLED; + } + + if (irq_status & DW_SPI_INT_RXFI) { + dw_reader(dws); + if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) + dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1); + } + + if (irq_status & DW_SPI_INT_TXEI) + dw_writer(dws); + + if (!dws->tx_len && dws->rx_len) { + dw_spi_mask_intr(dws, DW_SPI_INT_TXEI); + } else if (!dws->rx_len && !dws->tx_len) { + dw_spi_mask_intr(dws, 0xff); + spi_finalize_current_transfer(dws->ctlr); + } + + return IRQ_HANDLED; +} + static irqreturn_t dw_spi_irq(int irq, void *dev_id) { struct spi_controller *ctlr = dev_id; @@ -257,8 +285,15 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) if (!irq_status) return IRQ_NONE; - if (!ctlr->cur_msg) { + if (!ctlr->cur_msg && dws->transfer_handler == + dw_spi_transfer_handler) { + dw_spi_mask_intr(dws, 0xff); + return IRQ_HANDLED; + } + if (dws->transfer_handler == dw_spi_enh_handler && + !dws->rx_len && !dws->tx_len) { dw_spi_mask_intr(dws, 0xff); + spi_finalize_current_transfer(ctlr); return IRQ_HANDLED; } @@ -399,6 +434,34 @@ static void dw_spi_irq_setup(struct dw_spi *dws) dw_spi_umask_intr(dws, imask); } +static void dw_spi_enh_irq_setup(struct dw_spi *dws) +{ + u16 level; + u8 imask; + + /* + * Originally Tx and Rx data lengths match. Rx FIFO Threshold level + * will be adjusted at the final stage of the IRQ-based SPI transfer + * execution so not to lose the leftover of the incoming data. + */ + level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len); + dw_writel(dws, DW_SPI_TXFTLR, level); + + /* + * In enhanced mode if we are reading then tx_len is 0 as we + * have nothing to transmit. Calculate DW_SPI_RXFTLR with + * rx_len. + */ + level = min_t(unsigned int, dws->fifo_len / 2, dws->rx_len); + dw_writel(dws, DW_SPI_RXFTLR, level - 1); + + dws->transfer_handler = dw_spi_enh_handler; + + imask = DW_SPI_INT_TXEI | DW_SPI_INT_TXOI | + DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI; + dw_spi_umask_intr(dws, imask); +} + /* * The iterative procedure of the poll-based transfer is simple: write as much * as possible to the Tx FIFO, wait until the pending to receive data is ready @@ -855,6 +918,7 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op * struct dw_spi *dws = spi_controller_get_devdata(ctlr); struct dw_spi_enh_cfg enh_cfg; struct dw_spi_cfg cfg; + unsigned long long ms; switch (op->data.buswidth) { case 0: @@ -906,9 +970,36 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op * dw_spi_update_config(dws, mem->spi, &cfg, &enh_cfg); + dw_spi_mask_intr(dws, 0xff); + reinit_completion(&ctlr->xfer_completion); dw_spi_enable_chip(dws, 1); dw_spi_enh_write_cmd_addr(dws, op); + dw_spi_set_cs(mem->spi, false); + + udelay(5); + + dw_spi_enh_irq_setup(dws); + + /* Use timeout calculation from spi_transfer_wait() */ + ms = 8LL * MSEC_PER_SEC * (dws->rx_len ? dws->rx_len : dws->tx_len); + do_div(ms, dws->current_freq); + + /* + * Increase it twice and add 200 ms tolerance, use + * predefined maximum in case of overflow. + */ + ms += ms + 200; + if (ms > UINT_MAX) + ms = UINT_MAX; + + ms = wait_for_completion_timeout(&ctlr->xfer_completion, + msecs_to_jiffies(ms)); + + dw_spi_stop_mem_op(dws, mem->spi); + + if (ms == 0) + return -EIO; return 0; } -- 2.25.1