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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3140e6f0dcdsm6407084eec.31.2026.07.15.22.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 22:43:14 -0700 (PDT) From: Md Sadre Alam Date: Thu, 16 Jul 2026 11:13:05 +0530 Subject: [PATCH] spi: spi-qpic-snand: Increase ECC strength for large OOB SPI-NAND devices Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260716-8bitecc-v1-1-6eef4bcc3a14@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAGhvWGoC/y3MwQqDMBCE4VcJe+5CTDFWX6V4MHHa7sHYJrEI4 rsbao//MHwbJURBok5tFPGVJHMoUV0U+dcQnmAZS5PRxuqmsnxzkuE9u9bhOho0ttVU3u+Ih6w /6d6fHfFZCpjPkdyQwH6eJsmdClgz/9Ga+n0/ANBbfYKKAAAA X-Change-ID: 20260716-8bitecc-b9be3d2e7690 To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Md Sadre Alam X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE2MDA1NiBTYWx0ZWRfX8JKyE5Aidb8A iMeBYbD2vCvrlRKmqbOit3jvMnyKWoTYReN1aPdWtZArlrE4E4I3gvWuUaa7oC67YuLn4DhpDfv kB2wBrKK1d0rMnrCgn81UNRAuJfk3uovs6OfYWGJR80Qb4ui1qa9YtGf8bx1C+xyd1U6iHiAW38 xAKzj+zE3XhcE52aVDGyvrxqgiOBbxEASIATpHvUgOa/shfJUTmDd66ld70Mdxbj5czOi+WvzLY rz77vbW3FGOSGylacxLVpmoO1fj4IfUrrHiAN1FmYg1QbJbyr98Kuuvl85pl2YFYJGLVSO3S+Ue LQYX2dwgnt+6NqQhll+D3h0qsiUsRv/LHDARKbAfnp/RGFnRRiRGGI2FVCQfyg/nhQmHaKtWTrN rreOHa4SZOaxr/f/C4ghxT6NWhvhM6nyY7Y/0h5kJGWESNDKNVcnOFM8upgpy7JHGb5UyKxhbMk M3hU9OYW8UlOa4+7STw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE2MDA1NiBTYWx0ZWRfXy8g5HTafKdP5 PqR/lufwUHtaKIaXjoeeG6aPhT0Wct8hj9YabbfUXpDpT8CZmUp67wHxHyDK/vjLa5GihBzhFC0 3nr/pPUhKpMR811d5r+u+O6s82cUmlU= X-Proofpoint-GUID: iyyTUXIe-cEHjxVctrMUBKWfkqU2OJMT X-Proofpoint-ORIG-GUID: iyyTUXIe-cEHjxVctrMUBKWfkqU2OJMT X-Authority-Analysis: v=2.4 cv=SsOgLvO0 c=1 sm=1 tr=0 ts=6a586f74 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=-NaL9wa4eaIqG_6P2MEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_02,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607160056 Some SPI-NAND devices with large OOB areas require a stronger ECC configuration than the default one provided through firmware description. For example, Macronix devices with a 256-byte OOB area report that 4-bit ECC is insufficient and trigger: nand: WARNING: the ECC used on your system is too weak compared to the one required by the NAND chip The QPIC SPI-NAND controller supports both 4-bit and 8-bit BCH ECC modes. When a device exposes an OOB area of at least 128 bytes, there is sufficient space to accommodate 8-bit ECC without exceeding the OOB layout constraints. Automatically increase the ECC strength to 8 bits when the detected OOB size is 128 bytes or larger and the current configuration requests a weaker ECC level. This avoids ECC capability mismatches on devices that require stronger error correction and improves reliability. Signed-off-by: Md Sadre Alam --- drivers/spi/spi-qpic-snand.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 6cc53586b8a8..19812400124f 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -274,6 +274,19 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) ecc_cfg->strength = 4; } + /* + * Override ECC strength based on OOB size to avoid weak ECC warning. + * If OOB size is more than 128 bytes, use 8-bit ECC for better + * error correction capability, which is required by chips with + * larger OOB areas like Macronix SPI NAND with 256 bytes OOB. + */ + if (mtd->oobsize >= 128 && ecc_cfg->strength < 8) { + dev_info(snandc->dev, + "Upgrading ECC strength from %d to 8 bits (OOB size: %d bytes)\n", + ecc_cfg->strength, mtd->oobsize); + ecc_cfg->strength = 8; + } + if (ecc_cfg->step_size != NANDC_STEP_SIZE) { dev_err(snandc->dev, "only %u bytes ECC step size is supported\n", --- base-commit: 19827e7930a5511c68e12aac6e4522f3661a1709 change-id: 20260716-8bitecc-b9be3d2e7690 Best regards, -- Md Sadre Alam