[PATCH v2 0/2] spi: pxa2xx: MacBook8,1 quirk and LPSS S3 resume state fixes

["Shih-Yuan Lee (FourDollars)" <fourdollars@gmail.com>]

From: Shih-Yuan Lee <fourdollars@debian.org>

Hi Mark,

This patch series resolves two issues in the spi-pxa2xx host controller driver
related to Intel LPSS SPI controllers.

Patch 1 moves the forced PIO mode quirk for the Apple MacBook8,1 LPSS SPI
controller from the client driver (applespi) to the host controller PCI glue
driver (spi-pxa2xx-pci) where it belongs. It also fixes a runtime PM issue:
when DMA is disabled, aggressive runtime clock gating causes PCIe Completion
Timeouts on subsequent MMIO accesses. The fix is to only call pm_runtime_allow()
if DMA is enabled.

Patch 2 fixes S3 suspend/resume for Intel LPSS SPI controllers. The LPSS
power domain is fully removed across S3, losing all private register state.
Accessing MMIO on resume while the block is held in reset causes a PCIe Completion
Timeout and a watchdog system reset. To fix this, we save the LPSS private
registers in struct driver_data during suspend, de-assert resets first on
resume, and restore the saved registers.

Changes in v2:
  - Addressed feedback from Mark Brown.
  - Used drv_data->lpss_base together with relative offsets rather than
    hardcoding absolute MMIO offsets that vary between LPSS IP revisions.
  - Moved the register save block in suspend to after the controller is quiesced
    (after spi_controller_suspend() and pxa_ssp_disable()).
  - Store the context array lpss_priv_ctx[6] inside struct driver_data instead of
    struct pxa2xx_spi_controller. This keeps the changes entirely local to the
    core driver, preventing symbol version mismatches (disagrees about version
    of symbol) for other subsystem components (e.g., spi-pxa2xx-platform.ko).
  - Restrict the save/restore loop to the first 6 LPSS private registers
    (offsets 0x00 to 0x14). Offsets beyond 0x14 (except CS control at 0x18, which is
    re-initialised by lpss_ssp_setup()) are reserved/unimplemented on LPT
    platforms (such as MacBook8,1), and writing to them triggers a PCIe
    Completion Timeout causing a system freeze.
  - Added named constants for LPSS_PRIV_RESETS and the de-assert value.
  - Wrapped S3 suspend/resume with pm_runtime_resume_and_get() and
    pm_runtime_put_autosuspend() respectively. This ensures the controller is
    temporarily runtime-resumed to active state prior to suspend, guaranteeing
    the clock and power domain are active during MMIO register access, and that
    the private registers are consistently saved and restored across S3 sleep.
  - Permanently lock out runtime PM in pxa2xx_spi_probe() via pm_runtime_forbid()
    when DMA is disabled. This covers both static PIO and dynamic fallback to PIO
    and prevents userspace/udev from overriding the setting.
  - Call synchronize_irq() in pxa2xx_spi_runtime_suspend() to wait for active
    handlers on the shared interrupt line to finish before disabling the clock,
    avoiding unclocked MMIO register reads in ssp_int().
  - Avoid duplicate can-DMA pci_info() logging by checking the pre-computed
    enable_dma status in probe and passing a verbose flag to can_dma().

Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331

Shih-Yuan Lee (2):
  spi: pxa2xx: disable DMA and fix runtime PM for Apple MacBook8,1
  spi: pxa2xx: restore LPSS private register state on S3 resume

 drivers/spi/spi-pxa2xx-pci.c | 38 +++++++++++++++++++++++--
 drivers/spi/spi-pxa2xx.c     | 55 +++++++++++++++++++++++++++++++++++-
 drivers/spi/spi-pxa2xx.h     |  1 +
 3 files changed, 90 insertions(+), 4 deletions(-)

-- 
2.39.5