From: Jisheng Zhang <jszhang@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/3] spi: dw: use DW_SPI_INT_MASK instead of hardcoded 0xff
Date: Mon, 3 Aug 2026 22:06:48 +0800 [thread overview]
Message-ID: <20260803140649.12718-3-jszhang@kernel.org> (raw)
In-Reply-To: <20260803140649.12718-1-jszhang@kernel.org>
The Interrupt Mask Register valid bits is bit[5:0] which is well
defined with DW_SPI_INT_MASK, use it instead of the incorrect(but no
harm) and hardcoded 0xff.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/spi/spi-dw-core.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index f0d5528a0e8a..460e77b34ed9 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -228,7 +228,7 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
*/
dw_reader(dws);
if (!dws->rx_len) {
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
spi_finalize_current_transfer(dws->ctlr);
} else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
@@ -258,7 +258,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
return IRQ_NONE;
if (!ctlr->cur_msg) {
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
return IRQ_HANDLED;
}
@@ -445,7 +445,7 @@ static int dw_spi_transfer_one(struct spi_controller *ctlr,
dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
/* For poll mode just disable all interrupts */
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
if (dws->dma_mapped) {
ret = dws->dma_ops->dma_setup(dws, transfer);
@@ -706,7 +706,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
dw_spi_update_config(dws, mem->spi, &cfg);
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
dw_spi_enable_chip(dws, 1);
--
2.53.0
next prev parent reply other threads:[~2026-08-03 14:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-03 14:06 [PATCH v2 0/3] spi: dw: use threaded interrupt Jisheng Zhang
2026-08-03 14:06 ` [PATCH v2 1/3] spi: dw: use DW_SPI_ISR directly Jisheng Zhang
2026-08-03 14:06 ` Jisheng Zhang [this message]
2026-08-03 14:06 ` [PATCH v2 3/3] spi: dw: use threaded interrupt and optimize the threaded ISR Jisheng Zhang
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