From: Jisheng Zhang <jszhang@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/4] spi: cadence-xspi: only use readsq/writesq under 64BIT
Date: Mon, 3 Aug 2026 22:07:27 +0800 [thread overview]
Message-ID: <20260803140728.12747-4-jszhang@kernel.org> (raw)
In-Reply-To: <20260803140728.12747-1-jszhang@kernel.org>
Currently, cadence-xspi depends on 64BIT. This dependency isn't from
cadence xspi controller itself, but from marvell support code and 64bit
slave dma interface performance optimization.
readsq and writesq are only available under 64BIT. For 32BIT platforms,
we can fallback to ioread32_rep/iowrite32_rep. So we can remove another
reason of the 64BIT dependency.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/spi/spi-cadence-xspi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 784619f17b40..39c868a5b171 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -454,18 +454,20 @@ static inline void cdns_xspi_sdma_read(struct cdns_xspi_dev *cdns_xspi, size_t l
void *buf = cdns_xspi->in_buffer;
size_t offset = 0;
- if (cdns_xspi->dma_data_width == 4) {
+ if (!IS_ENABLED(CONFIG_64BIT) || cdns_xspi->dma_data_width == 4) {
if (IS_ALIGNED((uintptr_t)src, 4) && IS_ALIGNED((uintptr_t)buf, 4)) {
ioread32_rep(src, buf, len >> 2);
offset = len & ~0x3;
len -= offset;
}
+#ifdef CONFIG_64BIT
} else {
if (IS_ALIGNED((uintptr_t)src, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
readsq(src, buf, len >> 3);
offset = len & ~0x7;
len -= offset;
}
+#endif
}
ioread8_rep(src, (u8 *)buf + offset, len);
}
@@ -476,18 +478,20 @@ static inline void cdns_xspi_sdma_write(struct cdns_xspi_dev *cdns_xspi, size_t
const void *buf = cdns_xspi->out_buffer;
size_t offset = 0;
- if (cdns_xspi->dma_data_width == 4) {
+ if (!IS_ENABLED(CONFIG_64BIT) || cdns_xspi->dma_data_width == 4) {
if (IS_ALIGNED((uintptr_t)dst, 4) && IS_ALIGNED((uintptr_t)buf, 4)) {
iowrite32_rep(dst, buf, len >> 2);
offset = len & ~0x3;
len -= offset;
}
+#ifdef CONFIG_64BIT
} else {
if (IS_ALIGNED((uintptr_t)dst, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
writesq(dst, buf, len >> 3);
offset = len & ~0x7;
len -= offset;
}
+#endif
}
iowrite8_rep(dst, (const u8 *)buf + offset, len);
}
--
2.53.0
next prev parent reply other threads:[~2026-08-03 14:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-03 14:07 [PATCH 0/4] spi: cadence-xspi: remove 64BIT dependency Jisheng Zhang
2026-08-03 14:07 ` [PATCH 1/4] spi: cadence-xspi: group marvell support code together Jisheng Zhang
2026-08-03 14:07 ` [PATCH 2/4] spi: cadence-xspi: put marvell support code under CONFIG_64BIT Jisheng Zhang
2026-08-03 14:07 ` Jisheng Zhang [this message]
2026-08-03 14:07 ` [PATCH 4/4] spi: cadence-xspi: remove 64BIT Kconfig dependency Jisheng Zhang
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