[PATCH 6.12.y] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers

[Mehmet Fide <mehmet.fide@gmail.com>]

Please consider commit cac7e5054115 ("spi: spi-fsl-dspi: Avoid setup_accel
logic for DMA transfers") for 6.12.y. It is in mainline since v6.17 and
applies cleanly to 6.12.y.

It went in as a cleanup, so it carries neither a Fixes: tag nor a stable
tag, but on vf610 the logic it removes corrupts data in DMA mode, in two
ways:

1. For an odd number of bytes the accel logic packs into 16 bit frames and
   computes the word count as len / 2, so a 5 byte transfer puts 4 bytes in
   the first DMA transfer and leaves the last byte to a second one with
   different timing.

2. With SPI_LSB_FIRST the accel helpers byte swap through cpu_to_be16(),
   which combines with the hardware LSBFE bit and puts multi byte transfers
   on the wire in the wrong byte order.

Both are visible on a Colibri VF50 (vf610, DSPI in DMA mode), and both go
away with this commit, which is what we have been carrying locally against
6.12 to get correct transfers. Every stable tree older than 6.17 is
affected in the same way.

Thanks,
Mehmet