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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4f46bb550sm5016692a91.5.2026.10.01.06.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 06:18:29 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v2 1/3] spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller Date: Thu, 1 Oct 2026 21:18:16 +0800 Message-Id: <20261001131818.110028-2-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261001131818.110028-1-cwweng.linux@gmail.com> References: <20261001131818.110028-1-cwweng.linux@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chi-Wen Weng Extend the existing MA35D1 QSPI binding to also describe the MA35D1 SPI controller. The SPI and QSPI controllers are separate hardware IPs. QSPI additionally supports dual, quad and DTR transfers and a target-mode timeout function, but these differences do not require additional controller-specific Devicetree properties. Both controllers expose the same Devicetree-visible resources and provide up to two native chip-select signals. GPIO chip selects are supported through the generic SPI controller binding. Since the MA35D1 QSPI driver now supports GPIO chip selects, also remove the existing restriction on cs-gpios for the QSPI compatible. Add the nuvoton,ma35d1-spi compatible and update the binding description and examples to cover both controllers. Signed-off-by: Chi-Wen Weng --- .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 41 +++++++++++++++++-- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml index 40965ec5163b..72f2e1e1219a 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml @@ -4,7 +4,17 @@ $id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Nuvoton MA35D1 Quad SPI Controller +title: Nuvoton MA35D1 SPI and Quad SPI Controllers + +description: | + The Nuvoton MA35D1 SoC contains separate SPI and QSPI controller IPs. + Both controllers expose the same Devicetree-visible resources and provide + two native chip-select signals. GPIO chip selects are supported through the + generic SPI controller binding. + + The QSPI controller additionally supports dual, quad and DTR transfers and + a target-mode timeout function. These capability differences do not require + additional controller properties. maintainers: - Chi-Wen Weng @@ -14,7 +24,9 @@ allOf: properties: compatible: - const: nuvoton,ma35d1-qspi + enum: + - nuvoton,ma35d1-spi + - nuvoton,ma35d1-qspi reg: maxItems: 1 @@ -33,8 +45,6 @@ properties: maximum: 2 default: 2 - cs-gpios: false - required: - compatible - reg @@ -59,7 +69,30 @@ examples: interrupts = ; clocks = <&clk QSPI0_GATE>; resets = <&sys MA35D1_RESET_QSPI0>; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + spi@40600000 { + compatible = "nuvoton,ma35d1-spi"; + reg = <0 0x40600000 0 0x10000>; + interrupts = ; + clocks = <&clk SPI0_GATE>; + resets = <&sys MA35D1_RESET_SPI0>; + #address-cells = <1>; #size-cells = <0>; }; }; +... -- 2.25.1