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Wed, 11 Nov 2026 07:40:30 -0800 (PST) Received: from angelo-Precision-7550 ([94.154.175.53]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb4c5d831esm3899675e9.9.2026.11.11.07.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 07:40:29 -0800 (PST) From: Angelo Compagnucci To: Mark Brown , linux-spi@vger.kernel.org Cc: Ryan Wanner , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Angelo Compagnucci Subject: [PATCH 2/2] spi: atmel: allow changing bits_per_word between transfers Date: Wed, 11 Nov 2026 16:40:24 +0100 Message-ID: <20261111154024.543546-2-angelo.compagnucci@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261111154024.543546-1-angelo.compagnucci@gmail.com> References: <20261111154024.543546-1-angelo.compagnucci@gmail.com> X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The controller supports 8 to 16 bits per word, as its bits_per_word_mask says, but the word size is written in the chip select register only by setup(): a transfer with another word size fails with -ENOPROTOOPT ("you can't yet change bits_per_word in transfers"). The MIPI DBI panel drivers send commands in 8 bit words and pixels in 16 bit words when the controller supports them, so no frame reaches an ILI9341 panel on an Arietta G25 (SAM9G25): ili9341 spi0.0: SPI transfer failed: -92 The DMA and PIO paths already follow the word size of each transfer: when it differs from the configured one, update the BITS field of the chip select register instead of failing. Signed-off-by: Angelo Compagnucci --- drivers/spi/spi-atmel.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index fb8d4c7c9..c02a364fa 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1401,9 +1401,18 @@ static int atmel_spi_one_transfer(struct spi_controller *host, asd = spi->controller_state; bits = (asd->csr >> 4) & 0xf; if (bits != xfer->bits_per_word - 8) { - dev_dbg(&spi->dev, - "you can't yet change bits_per_word in transfers\n"); - return -ENOPROTOOPT; + int chip_select; + + if (spi_get_csgpiod(spi, 0)) + chip_select = as->native_cs_for_gpio; + else + chip_select = spi_get_chipselect(spi, 0); + + /* The chip select is active: only the word size changes */ + asd->csr = SPI_BFINS(BITS, xfer->bits_per_word - 8, asd->csr); + spi_writel(as, CSR0 + 4 * chip_select, asd->csr); + if (atmel_spi_is_v2(as)) + spi_writel(as, CSR0, asd->csr); } /* -- 2.53.0