From: Jon Hunter <jonathanh@nvidia.com>
To: Vishwaroop A <va@nvidia.com>, Mark Brown <broonie@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
Laxman Dewangan <ldewangan@nvidia.com>,
smangipudi@nvidia.com, kyarlagadda@nvidia.com
Cc: linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, Thierry Reding <treding@nvidia.com>
Subject: Re: [PATCH v2 1/2] spi: tegra210-quad: Fix timeout handling
Date: Thu, 16 Oct 2025 14:44:26 +0100 [thread overview]
Message-ID: <21078f4e-cb55-42c3-b3bc-2bdf8ce38aa2@nvidia.com> (raw)
In-Reply-To: <20251016132923.3577429-2-va@nvidia.com>
On 16/10/2025 14:29, Vishwaroop A wrote:
> When the CPU that the QSPI interrupt handler runs on (typically CPU 0)
> is excessively busy, it can lead to rare cases of the IRQ thread not
> running before the transfer timeout is reached.
>
> While handling the timeouts, any pending transfers are cleaned up and
> the message that they correspond to is marked as failed, which leaves
> the curr_xfer field pointing at stale memory.
>
> To avoid this, clear curr_xfer to NULL upon timeout and check for this
> condition when the IRQ thread is finally run.
>
> While at it, also make sure to clear interrupts on failure so that new
> interrupts can be run.
>
> A better, more involved, fix would move the interrupt clearing into a
> hard IRQ handler. Ideally we would also want to signal that the IRQ
> thread no longer needs to be run after the timeout is hit to avoid the
> extra check for a valid transfer.
>
> Fixes: 921fc1838fb0 ("spi: tegra210-quad: Add support for Tegra210 QSPI controller")
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Vishwaroop A <va@nvidia.com>
> ---
> drivers/spi/spi-tegra210-quad.c | 23 ++++++++++++++++++++---
> 1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
> index 3be7499db21e..10e56d8ef678 100644
> --- a/drivers/spi/spi-tegra210-quad.c
> +++ b/drivers/spi/spi-tegra210-quad.c
> @@ -1024,8 +1024,10 @@ static void tegra_qspi_handle_error(struct tegra_qspi *tqspi)
> dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg);
> tegra_qspi_dump_regs(tqspi);
> tegra_qspi_flush_fifos(tqspi, true);
> - if (device_reset(tqspi->dev) < 0)
> + if (device_reset(tqspi->dev) < 0) {
> dev_warn_once(tqspi->dev, "device reset failed\n");
> + tegra_qspi_mask_clear_irq(tqspi);
> + }
> }
>
> static void tegra_qspi_transfer_end(struct spi_device *spi)
> @@ -1173,12 +1175,14 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
> dma_ctl &= ~QSPI_DMA_EN;
> tegra_qspi_writel(tqspi, dma_ctl,
> QSPI_DMA_CTL);
> - }
> + }
The above does not look correct.
Jon
--
nvpublic
next prev parent reply other threads:[~2025-10-16 13:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 13:29 [PATCH v2 0/2] spi: tegra210-quad: Improve timeout handling under high system load Vishwaroop A
2025-10-16 13:29 ` [PATCH v2 1/2] spi: tegra210-quad: Fix timeout handling Vishwaroop A
2025-10-16 13:44 ` Jon Hunter [this message]
2025-10-16 15:14 ` Thierry Reding
2025-10-16 13:29 ` [PATCH v2 2/2] spi: tegra210-quad: Check hardware status on timeout Vishwaroop A
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