From: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
<linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Mark Brown <broonie@kernel.org>,
Conor Dooley - M52691 <Conor.Dooley@microchip.com>,
Prajna Rajendra Kumar - M74368
<prajna.rajendrakumar@microchip.com>
Subject: Re: [PATCH v2 4/6] spi: microchip-core: Utilise temporary variable for struct device
Date: Thu, 27 Nov 2025 15:59:54 +0000 [thread overview]
Message-ID: <39651aeb-668b-483c-b326-56adf38a7e63@microchip.com> (raw)
In-Reply-To: <20251126075558.2035012-5-andriy.shevchenko@linux.intel.com>
On 26/11/2025 07:54, Andy Shevchenko wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add a temporary variable to keep a pointer to struct device.
> Utilise it where it makes sense.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
> ---
> drivers/spi/spi-microchip-core-spi.c | 44 +++++++++++++---------------
> 1 file changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c
> index 8ea382c6fee7..0dca46dcdc2f 100644
> --- a/drivers/spi/spi-microchip-core-spi.c
> +++ b/drivers/spi/spi-microchip-core-spi.c
> @@ -284,6 +284,7 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
> static int mchp_corespi_probe(struct platform_device *pdev)
> {
> const char *protocol = "motorola";
> + struct device *dev = &pdev->dev;
> struct spi_controller *host;
> struct mchp_corespi *spi;
> struct resource *res;
> @@ -291,13 +292,13 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> bool assert_ssel;
> int ret = 0;
>
> - host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
> + host = devm_spi_alloc_host(dev, sizeof(*spi));
> if (!host)
> return -ENOMEM;
>
> platform_set_drvdata(pdev, host);
>
> - if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
> + if (of_property_read_u32(dev->of_node, "num-cs", &num_cs))
> num_cs = MCHP_CORESPI_MAX_CS;
>
> /*
> @@ -305,12 +306,12 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> * CoreSPI can be configured for Motorola, TI or NSC.
> * The current driver supports only Motorola mode.
> */
> - ret = of_property_read_string(pdev->dev.of_node, "microchip,protocol-configuration",
> + ret = of_property_read_string(dev->of_node, "microchip,protocol-configuration",
> &protocol);
> if (ret && ret != -EINVAL)
> - return dev_err_probe(&pdev->dev, ret, "Error reading protocol-configuration\n");
> + return dev_err_probe(dev, ret, "Error reading protocol-configuration\n");
> if (strcmp(protocol, "motorola") != 0)
> - return dev_err_probe(&pdev->dev, -EINVAL,
> + return dev_err_probe(dev, -EINVAL,
> "CoreSPI: protocol '%s' not supported by this driver\n",
> protocol);
>
> @@ -318,11 +319,11 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> * Motorola mode (0-3): CFG_MOT_MODE
> * Mode is fixed in the IP configurator.
> */
> - ret = of_property_read_u32(pdev->dev.of_node, "microchip,motorola-mode", &mode);
> + ret = of_property_read_u32(dev->of_node, "microchip,motorola-mode", &mode);
> if (ret)
> mode = MCHP_CORESPI_DEFAULT_MOTOROLA_MODE;
> else if (mode > 3)
> - return dev_err_probe(&pdev->dev, -EINVAL,
> + return dev_err_probe(dev, -EINVAL,
> "invalid 'microchip,motorola-mode' value %u\n", mode);
>
> /*
> @@ -330,9 +331,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> * The hardware allows frame sizes <= APB data width.
> * However, this driver currently only supports 8-bit frames.
> */
> - ret = of_property_read_u32(pdev->dev.of_node, "microchip,frame-size", &frame_size);
> + ret = of_property_read_u32(dev->of_node, "microchip,frame-size", &frame_size);
> if (!ret && frame_size != 8)
> - return dev_err_probe(&pdev->dev, -EINVAL,
> + return dev_err_probe(dev, -EINVAL,
> "CoreSPI: frame size %u not supported by this driver\n",
> frame_size);
>
> @@ -342,9 +343,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> * To prevent CS deassertion when TX FIFO drains, the ssel-active property
> * keeps CS asserted for the full SPI transfer.
> */
> - assert_ssel = of_property_read_bool(pdev->dev.of_node, "microchip,ssel-active");
> + assert_ssel = of_property_read_bool(dev->of_node, "microchip,ssel-active");
> if (!assert_ssel)
> - return dev_err_probe(&pdev->dev, -EINVAL,
> + return dev_err_probe(dev, -EINVAL,
> "hardware must enable 'microchip,ssel-active' to keep CS asserted for the SPI transfer\n");
>
> spi = spi_controller_get_devdata(host);
> @@ -356,9 +357,9 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
> host->transfer_one = mchp_corespi_transfer_one;
> host->set_cs = mchp_corespi_set_cs;
> - host->dev.of_node = pdev->dev.of_node;
> + host->dev.of_node = dev->of_node;
>
> - ret = of_property_read_u32(pdev->dev.of_node, "fifo-depth", &spi->fifo_depth);
> + ret = of_property_read_u32(dev->of_node, "fifo-depth", &spi->fifo_depth);
> if (ret)
> spi->fifo_depth = MCHP_CORESPI_DEFAULT_FIFO_DEPTH;
>
> @@ -370,24 +371,21 @@ static int mchp_corespi_probe(struct platform_device *pdev)
> if (spi->irq < 0)
> return spi->irq;
>
> - ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
> - IRQF_SHARED, dev_name(&pdev->dev), host);
> + ret = devm_request_irq(dev, spi->irq, mchp_corespi_interrupt, IRQF_SHARED,
> + dev_name(dev), host);
> if (ret)
> - return dev_err_probe(&pdev->dev, ret,
> - "could not request irq\n");
> + return dev_err_probe(dev, ret, "could not request irq\n");
>
> - spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
> + spi->clk = devm_clk_get_enabled(dev, NULL);
> if (IS_ERR(spi->clk))
> - return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
> - "could not get clk\n");
> + return dev_err_probe(dev, PTR_ERR(spi->clk), "could not get clk\n");
>
> mchp_corespi_init(host, spi);
>
> - ret = devm_spi_register_controller(&pdev->dev, host);
> + ret = devm_spi_register_controller(dev, host);
> if (ret) {
> mchp_corespi_disable(spi);
> - return dev_err_probe(&pdev->dev, ret,
> - "unable to register host for CoreSPI controller\n");
> + return dev_err_probe(dev, ret, "unable to register host for CoreSPI controller\n");
> }
>
> return 0;
> --
> 2.50.1
>
next prev parent reply other threads:[~2025-11-27 15:48 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 7:54 [PATCH v2 0/6] spi: microchip-core: Code improvements Andy Shevchenko
2025-11-26 7:54 ` [PATCH v2 1/6] spi: microchip-core: use min() instead of min_t() Andy Shevchenko
2025-11-26 9:22 ` david laight
2025-11-27 15:55 ` Prajna Rajendra Kumar
2025-11-26 7:54 ` [PATCH v2 2/6] spi: microchip-core: Refactor FIFO read and write handlers Andy Shevchenko
2025-11-26 9:21 ` david laight
2025-11-26 11:17 ` Andy Shevchenko
2025-11-26 12:05 ` Mark Brown
2025-11-26 12:13 ` Andy Shevchenko
2025-11-27 16:08 ` Prajna Rajendra Kumar
2025-11-27 16:49 ` Andy Shevchenko
2025-11-27 16:50 ` Andy Shevchenko
2025-11-27 18:05 ` Conor Dooley
2025-11-27 19:01 ` Andy Shevchenko
2025-11-26 7:54 ` [PATCH v2 3/6] spi: microchip-core: Replace dead code (-ENOMEM error message) Andy Shevchenko
2025-11-27 15:58 ` Prajna Rajendra Kumar
2025-11-26 7:54 ` [PATCH v2 4/6] spi: microchip-core: Utilise temporary variable for struct device Andy Shevchenko
2025-11-27 15:59 ` Prajna Rajendra Kumar [this message]
2025-11-26 7:54 ` [PATCH v2 5/6] spi: microchip-core: Use SPI_MODE_X_MASK Andy Shevchenko
2025-11-27 16:00 ` Prajna Rajendra Kumar
2025-11-26 7:54 ` [PATCH v2 6/6] spi: microchip-core: Remove unneeded PM related macro Andy Shevchenko
2025-11-27 16:01 ` Prajna Rajendra Kumar
2025-11-28 18:01 ` (subset) [PATCH v2 0/6] spi: microchip-core: Code improvements Mark Brown
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