From: Michal Simek <monstr@monstr.eu>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org
Subject: Re: [PATCH v6 0/3] Stacked/parallel memories bindings
Date: Fri, 18 Feb 2022 12:53:44 +0100 [thread overview]
Message-ID: <41049c30-aaf1-30e5-2d11-14df0b468411@monstr.eu> (raw)
In-Reply-To: <20220126112608.955728-1-miquel.raynal@bootlin.com>
Hi Mark
On 1/26/22 12:26, Miquel Raynal wrote:
> Hello Rob, Mark, Tudor & Pratyush,
>
> Here is a sixth versions for these bindings, which applies on top of
> the v5.17-rc1 now that Pratyush's work as been merged.
> (https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/)
>
> Cheers,
> Miquèl
>
> Changes in v6:
> * Added Pratyush's acks.
> * The tooling now validates the binding (updating dt-schema is
> necesary).
> * Updated the maxItems field to 4 as a "big enough value" as discussed.
>
> Changes in v5:
> * Used the uint64-array instead of the matrix type.
> * Updated the example as well to use a single "/bits/ 64" cast because
> doing it twice, despite being supported by the language itself, is not
> yet something that we can use for describing bindings.
>
> Changes in v4:
> * Changed the type of properties to uint64-arrays in order to be able to
> describe the size of each element in the array.
> * Updated the example accordingly.
>
> Changes in v3:
> * Rebased on top of Pratyush's recent changes.
> * Dropped the commit allowing to provide two reg entries on the node
> name.
> * Dropped the commit referencing spi-controller.yaml from
> jedec,spi-nor.yaml, now replaced by spi-peripheral-props.yaml and
> already done in Pratyush's series.
> * Added Rob's Ack.
> * Enhanced a commit message.
> * Moved the new properties to the new SPI peripheral binding file.
>
> Changes in v2:
> * Dropped the dtc changes for now.
> * Moved the properties in the device's nodes, not the controller's.
> * Dropped the useless #address-cells change.
> * Added a missing "minItems".
> * Moved the new properties in the spi-controller.yaml file.
> * Added an example using two stacked memories in the
> spi-controller.yaml file.
> * Renamed the properties to drop the Xilinx prefix.
> * Added a patch to fix the spi-nor jedec yaml file.
>
> Miquel Raynal (3):
> dt-bindings: mtd: spi-nor: Allow two CS per device
> spi: dt-bindings: Describe stacked/parallel memories modes
> spi: dt-bindings: Add an example with two stacked flashes
>
> .../bindings/mtd/jedec,spi-nor.yaml | 3 ++-
> .../bindings/spi/spi-controller.yaml | 7 ++++++
> .../bindings/spi/spi-peripheral-props.yaml | 25 +++++++++++++++++++
> 3 files changed, 34 insertions(+), 1 deletion(-)
>
Can you please pick up this series?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
next prev parent reply other threads:[~2022-02-18 11:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 11:26 [PATCH v6 0/3] Stacked/parallel memories bindings Miquel Raynal
2022-01-26 11:26 ` [PATCH v6 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal
2022-01-26 11:26 ` [PATCH v6 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal
2022-02-04 22:20 ` Rob Herring
2022-01-26 11:26 ` [PATCH v6 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal
2022-02-18 11:53 ` Michal Simek [this message]
2022-02-21 15:24 ` [PATCH v6 0/3] Stacked/parallel memories bindings Mark Brown
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