* [PATCH v5 0/1] davinci: spi: replace existing driver
@ 2010-07-28 22:18 Brian Niebuhr
[not found] ` <1280355490-11878-1-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org>
0 siblings, 1 reply; 33+ messages in thread
From: Brian Niebuhr @ 2010-07-28 22:18 UTC (permalink / raw)
To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f
Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/
Fixed in this version:
- Addressed all comments from the previous version
** NOTE **
This patch requires the EDMA patch at:
http://linux.davincidsp.com/pipermail/davinci-linux-open-source/2010-March/018022.html
which is queued waiting on another driver fix, for DMA mode to work correctly.
Brian Niebuhr (1):
davinci: spi: replace existing driver
arch/arm/mach-davinci/board-dm355-evm.c | 10 +
arch/arm/mach-davinci/board-dm355-leopard.c | 10 +
arch/arm/mach-davinci/board-dm365-evm.c | 10 +
arch/arm/mach-davinci/dm355.c | 8 +-
arch/arm/mach-davinci/dm365.c | 6 -
arch/arm/mach-davinci/include/mach/spi.h | 35 +-
drivers/spi/davinci_spi.c | 1098 ++++++++++++---------------
7 files changed, 521 insertions(+), 656 deletions(-)
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 33+ messages in thread[parent not found: <1280355490-11878-1-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org>]
* [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <1280355490-11878-1-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> @ 2010-07-28 22:18 ` Brian Niebuhr [not found] ` <1280355490-11878-2-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Brian Niebuhr @ 2010-07-28 22:18 UTC (permalink / raw) To: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f Cc: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ INTRODUCTION I have been working on a custom OMAP-L138 board that has multiple spi devices (seven) on one controller. These devices have a wide range of transfer parameters (speed, phase, polarity, internal and gpio chip selects). During my testing I found multiple errors in the davinci spi driver as a result of this complex setup. The primary issues were: 1. There is a race condition due to the SPIBUF read busy-waits for slow devices 2. I found some DMA transfer length errors under some conditions 3. The chip select code caused extra byte transfers (with no chip select active) due to writes to SPIDAT1 4. Several issues prevented using multiple SPI devices, especially the DMA code, as disucussed previously on the davinci list. The fixes to these problems were not simple. I ended up making fairly large changes to the driver, and those changes are contained in these patches. The full list of changes follows. CHANGE LIST 1. davinci_spi_chipelect() now performs both activation and deactivation of chip selects. This lets spi_bitbang fully control chip select activation, as intended by the SPI API. 2. Chip select activation does not cause extra writes to the SPI bus 3. Chip select activation does not use SPIDEF for control. This change will also allow for implementation of inverted (active high) chip selects in the future. 4. Added back gpio chip select capability from the old driver 5. Fixed prescale calculation for non-integer fractions of spi clock 6. Allow specification of SPI transfer parameters on a per-device (instead of per-controller) basis 7. Allow specification of polled, interrupt-based, or DMA operation on a per-device basis 8. Allow DMA with when more than one device is connected 9. Combined pio and dma txrx_bufs functions into one since they share large parts of their functionality, and to simplify item (8). 10. Use only SPIFMT0 to allow more than 4 devices TESTING I have tested the driver using a custom SPI stress test on my OMAP-L138-based board with three devices connected. I have tested configurations with all three devices polled, all three interrupt-based, all three DMA, and a mixture. I have compiled with the davinci_all_defconfig, but I don't have EVMs for the other davinci platforms to test with. Signed-off-by: Brian Niebuhr <bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> --- arch/arm/mach-davinci/board-dm355-evm.c | 10 + arch/arm/mach-davinci/board-dm355-leopard.c | 10 + arch/arm/mach-davinci/board-dm365-evm.c | 10 + arch/arm/mach-davinci/dm355.c | 8 +- arch/arm/mach-davinci/dm365.c | 6 - arch/arm/mach-davinci/include/mach/spi.h | 35 +- drivers/spi/davinci_spi.c | 1098 ++++++++++++--------------- 7 files changed, 521 insertions(+), 656 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a319101..ad8779b 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -32,6 +32,7 @@ #include <mach/nand.h> #include <mach/mmc.h> #include <mach/usb.h> +#include <mach/spi.h> /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index f1d8132..b2d8d48 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -29,6 +29,7 @@ #include <mach/nand.h> #include <mach/mmc.h> #include <mach/usb.h> +#include <mach/spi.h> /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640a_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm355_leopard_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640a, + .controller_data = &at25640a_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5bb86b2..db85372 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -39,6 +39,7 @@ #include <mach/mmc.h> #include <mach/nand.h> #include <mach/keyscan.h> +#include <mach/spi.h> #include <media/tvp514x.h> @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; +static struct davinci_spi_config at25640_spi_cfg = { + .parity_enable = false, + .intr_level = 0, + .io_type = SPI_IO_TYPE_DMA, + .wdelay = 0, + .timer_disable = true, +}; + static struct spi_board_info dm365_evm_spi_info[] __initconst = { { .modalias = "at25", .platform_data = &at25640, + .controller_data = &at25640_spi_cfg, .max_speed_hz = 10 * 1000 * 1000, .bus_num = 0, .chip_select = 0, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 3834781..b79b798 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { }; static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, + .version = SPI_VERSION_0, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct platform_device dm355_spi0_device = { .name = "spi_davinci", diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 652f4b6..4aea346 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); static struct davinci_spi_platform_data dm365_spi0_pdata = { .version = SPI_VERSION_1, .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .c2tdelay = 0, - .t2cdelay = 0, }; static struct resource dm365_spi0_resources[] = { diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf..3f77dab 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,26 +19,35 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ SPI_VERSION_2, /* For DA8xx */ }; struct davinci_spi_platform_data { u8 version; - u8 num_chipselect; - u8 wdelay; - u8 odd_parity; - u8 parity_enable; - u8 wait_enable; - u8 timer_disable; - u8 clk_internal; - u8 cs_hold; + u16 num_chipselect; + u8 *chip_sel; +}; + +struct davinci_spi_config { + bool odd_parity; + bool parity_enable; u8 intr_level; - u8 poll_mode; - u8 use_dma; - u8 c2tdelay; - u8 t2cdelay; + u8 io_type; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 bytes_per_word; + u8 wdelay; + bool timer_disable; + u8 c2t_delay; + u8 t2c_delay; + u8 t2e_delay; + u8 c2e_delay; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index b85090c..5c9e9ce 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2010 EF Johnson Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,21 +28,19 @@ #include <linux/dma-mapping.h> #include <linux/spi/spi.h> #include <linux/spi/spi_bitbang.h> -#include <linux/slab.h> #include <mach/spi.h> #include <mach/edma.h> #define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 - #define CS_DEFAULT 0xFF #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 + +#define RX_DMA_INDEX 0 +#define TX_DMA_INDEX 1 +#define EVENTQ_DMA_INDEX 2 #define SPIFMT_PHASE_MASK BIT(16) #define SPIFMT_POLARITY_MASK BIT(17) @@ -53,9 +52,11 @@ #define SPIFMT_WDELAY_MASK 0x3f000000u #define SPIFMT_WDELAY_SHIFT 24 #define SPIFMT_CHARLEN_MASK 0x0000001Fu +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIGCR1 */ -#define SPIGCR1_SPIENA_MASK 0x01000000u +#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) /* SPIPC0 */ #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ @@ -66,20 +67,38 @@ #define SPIPC0_EN0FUN_MASK BIT(0) #define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000035F #define SPI_INTLVL_1 0x000001FFu #define SPI_INTLVL_0 0x00000000u /* SPIDAT1 */ +#define SPIDAT1_CSHOLD_MASK BIT(28) #define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_WDEL_MASK BIT(26) +#define SPIDAT1_CSNR_MASK 0x00FF0000u #define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) #define SPIGCR1_CLKMOD_MASK BIT(1) -#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_MASTER_MASK BIT(0) #define SPIGCR1_LOOPBACK_MASK BIT(16) /* SPIBUF */ #define SPIBUF_TXFULL_MASK BIT(29) #define SPIBUF_RXEMPTY_MASK BIT(31) +/* SPIDELAY */ +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u +#define SPIDELAY_C2TDELAY_SHIFT 24 +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u +#define SPIDELAY_T2CDELAY_SHIFT 16 +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u +#define SPIDELAY_T2EDELAY_SHIFT 8 +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu +#define SPIDELAY_C2EDELAY_SHIFT 0 + +/* SPIDEF */ +#define SPIDEF_CSDEF_MASK 0x000000FFu + /* Error Masks */ #define SPIFLG_DLEN_ERR_MASK BIT(0) #define SPIFLG_TIMEOUT_MASK BIT(1) @@ -90,11 +109,12 @@ #define SPIFLG_RX_INTR_MASK BIT(8) #define SPIFLG_TX_INTR_MASK BIT(9) #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ - | SPIFLG_TX_INTR_MASK \ + | SPIFLG_OVRRUN_MASK) +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ | SPIFLG_BUF_INIT_ACTIVE_MASK) #define SPIINT_DLEN_ERR_INTR BIT(0) @@ -139,11 +159,10 @@ #define TGINTVEC0 0x60 #define TGINTVEC1 0x64 -struct davinci_spi_slave { - u32 cmd_to_write; - u32 clk_ctrl_to_write; - u32 bytes_per_word; - u8 active_cs; +const char * const io_type_names[] = { + [SPI_IO_TYPE_INTR] = "Interrupt", + [SPI_IO_TYPE_POLL] = "Polled", + [SPI_IO_TYPE_DMA] = "DMA", }; /* We have 2 DMA channels per CS, one for RX and one for TX */ @@ -152,10 +171,8 @@ struct davinci_spi_dma { int dma_rx_channel; int dma_tx_sync_dev; int dma_rx_sync_dev; + int dummy_param_slot; enum dma_event_q eventq; - - struct completion dma_tx_completion; - struct completion dma_rx_completion; }; /* SPI Controller driver's private data. */ @@ -173,51 +190,53 @@ struct davinci_spi { const void *tx; void *rx; u8 *tmp_buf; - int count; - struct davinci_spi_dma *dma_channels; - struct davinci_spi_platform_data *pdata; + int rcount; + int wcount; + u32 errors; + struct davinci_spi_dma dma_channels; + struct davinci_spi_platform_data *pdata; void (*get_rx)(u32 rx_data, struct davinci_spi *); u32 (*get_tx)(struct davinci_spi *); - - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; }; -static unsigned use_dma; - static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) { - u8 *rx = davinci_spi->rx; - - *rx++ = (u8)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u8 *rx = davinci_spi->rx; + *rx++ = (u8)data; + davinci_spi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) { - u16 *rx = davinci_spi->rx; - - *rx++ = (u16)data; - davinci_spi->rx = rx; + if (davinci_spi->rx) { + u16 *rx = davinci_spi->rx; + *rx++ = (u16)data; + davinci_spi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) { - u32 data; - const u8 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u8 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) { - u32 data; - const u16 *tx = davinci_spi->tx; - - data = *tx++; - davinci_spi->tx = tx; + u32 data = 0; + if (davinci_spi->tx) { + const u16 *tx = davinci_spi->tx; + data = *tx++; + davinci_spi->tx = tx; + } return data; } @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) iowrite32(v, addr); } -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) -{ - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); -} - -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) -{ - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); - - if (enable) - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); - else - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); -} - /* * Interface to control the chip select signal */ @@ -264,25 +263,54 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; - u32 data1_reg_val = 0; + u8 i, chip_sel = spi->chip_select; + u32 spidat1; + u16 spidat1_cfg; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + spidat1 = SPIDAT1_CSNR_MASK; + if (value == BITBANG_CS_ACTIVE) + spidat1 |= SPIDAT1_CSHOLD_MASK; + else + spidat1 |= SPIDAT1_WDEL_MASK; - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); + if (pdata->chip_sel == NULL) { + if (value == BITBANG_CS_ACTIVE) + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); + } else { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] == SPI_INTERN_CS) { + if ((i == chip_sel) && + (value == BITBANG_CS_ACTIVE)) { + spidat1 &= ~((0x1 << chip_sel) + << SPIDAT1_CSNR_SHIFT); + } + } else { + if (value == BITBANG_CS_INACTIVE) + gpio_set_value(pdata->chip_sel[i], 1); + else if (i == chip_sel) + gpio_set_value(pdata->chip_sel[i], 0); + } + } } + + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); +} + +/** + * davinci_spi_get_prescale - Calculates the correct prescale value + * @max_speed_hz: the maximum rate the SPI clock can run at + * + * This function calculates the prescale value that generates a clock rate + * less than or equal to the specified maximum + */ +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, + u32 max_speed_hz) +{ + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; } /** @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) static int davinci_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { - struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; u8 bits_per_word = 0; - u32 hz = 0, prescale = 0, clkspeed; + u32 hz = 0, spifmt = 0, prescale, delay = 0; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + spi_cfg = spi->controller_data; if (t) { bits_per_word = t->bits_per_word; @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; + spi_cfg->bytes_per_word = 1; } else if (bits_per_word <= 16 && bits_per_word >= 2) { davinci_spi->get_rx = davinci_spi_rx_buf_u16; davinci_spi->get_tx = davinci_spi_tx_buf_u16; - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; + spi_cfg->bytes_per_word = 2; } else return -EINVAL; if (!hz) hz = spi->max_speed_hz; - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, - spi->chip_select); + prescale = davinci_spi_get_prescale(davinci_spi, hz); + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); + + spifmt |= (bits_per_word & 0x1f); + + if (spi->mode & SPI_LSB_FIRST) + spifmt |= SPIFMT_SHIFTDIR_MASK; + + if (spi->mode & SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; + + if (!(spi->mode & SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; + + if (davinci_spi->version == SPI_VERSION_2) { + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); + + if (spi_cfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; + + if (spi_cfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; + + if (spi->mode & SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spi_cfg->t2e_delay + << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spi_cfg->c2e_delay + << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } + + if (spi_cfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spi_cfg->c2t_delay + << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spi_cfg->t2c_delay + << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } - clkspeed = clk_get_rate(davinci_spi->clk); - if (hz > clkspeed / 2) - prescale = 1 << 8; - if (hz < clkspeed / 256) - prescale = 255 << 8; - if (!prescale) - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; + iowrite32(delay, davinci_spi->base + SPIDELAY); + } + + iowrite32(spifmt, davinci_spi->base + SPIFMT0); - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); + if (spi_cfg->intr_level) + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); + else + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + + if (spi->mode & SPI_LOOP) + set_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(davinci_spi->base + SPIGCR1, + SPIGCR1_LOOPBACK_MASK); return 0; } static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; + edma_stop(davinci_spi_dma->dma_rx_channel); + if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_rx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi->rcount = 0; - complete(&davinci_spi_dma->dma_rx_completion); - /* We must disable the DMA RX request */ - davinci_spi_set_dma_req(spi, 0); + complete(&davinci_spi->done); } static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) { - struct spi_device *spi = (struct spi_device *)data; - struct davinci_spi *davinci_spi; + struct davinci_spi *davinci_spi = data; struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_platform_data *pdata; - davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); + davinci_spi_dma = &(davinci_spi->dma_channels); pdata = davinci_spi->pdata; - if (ch_status == DMA_COMPLETE) - edma_stop(davinci_spi_dma->dma_tx_channel); - else - edma_clean_channel(davinci_spi_dma->dma_tx_channel); + edma_stop(davinci_spi_dma->dma_tx_channel); - complete(&davinci_spi_dma->dma_tx_completion); - /* We must disable the DMA TX request */ - davinci_spi_set_dma_req(spi, 0); + if (ch_status == DMA_COMPLETE) + davinci_spi->wcount = 0; } static int davinci_spi_request_dma(struct spi_device *spi) @@ -403,30 +468,51 @@ static int davinci_spi_request_dma(struct spi_device *spi) int r; davinci_spi = spi_master_get_devdata(spi->master); - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; + davinci_spi_dma = &davinci_spi->dma_channels; pdata = davinci_spi->pdata; sdev = davinci_spi->bitbang.master->dev.parent; r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, - davinci_spi_dma_rx_callback, spi, + davinci_spi_dma_rx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); + r = -EAGAIN; + goto rx_dma_failed; } davinci_spi_dma->dma_rx_channel = r; + r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, - davinci_spi_dma_tx_callback, spi, + davinci_spi_dma_tx_callback, davinci_spi, davinci_spi_dma->eventq); if (r < 0) { - edma_free_channel(davinci_spi_dma->dma_rx_channel); - davinci_spi_dma->dma_rx_channel = -1; - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); - return -EAGAIN; + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); + r = -EAGAIN; + goto tx_dma_failed; } davinci_spi_dma->dma_tx_channel = r; + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), + EDMA_SLOT_ANY); + if (r < 0) { + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); + r = -EAGAIN; + goto param_failed; + } + davinci_spi_dma->dummy_param_slot = r; + edma_link(davinci_spi_dma->dummy_param_slot, + davinci_spi_dma->dummy_param_slot); + return 0; + +param_failed: + edma_free_channel(davinci_spi_dma->dma_tx_channel); + davinci_spi_dma->dma_tx_channel = -1; +tx_dma_failed: + edma_free_channel(davinci_spi_dma->dma_rx_channel); + davinci_spi_dma->dma_rx_channel = -1; +rx_dma_failed: + return r; } /** @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) static int davinci_spi_setup(struct spi_device *spi) { - int retval; + int retval = 0; struct davinci_spi *davinci_spi; - struct davinci_spi_dma *davinci_spi_dma; - struct device *sdev; + struct davinci_spi_dma *davinci_dma; + struct davinci_spi_platform_data *pdata; + struct davinci_spi_config *spi_cfg; + u32 prescale; davinci_spi = spi_master_get_devdata(spi->master); - sdev = davinci_spi->bitbang.master->dev.parent; + pdata = davinci_spi->pdata; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); /* if bits per word length is zero then set it default 8 */ if (!spi->bits_per_word) spi->bits_per_word = 8; - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(davinci_spi->base + SPIPC0, + 1 << spi->chip_select); - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel == -1) - || (davinci_spi_dma->dma_tx_channel == -1)) { - retval = davinci_spi_request_dma(spi); - if (retval < 0) - return retval; - } - } - - /* - * SPI in DaVinci and DA8xx operate between - * 600 KHz and 50 MHz - */ - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { - dev_dbg(sdev, "Operating frequency is not in acceptable " - "range\n"); - return -EINVAL; } - /* - * Set up SPIFMTn register, unique to this chipselect. - * - * NOTE: we could do all of these with one write. Also, some - * of the "version 2" features are found in chips that don't - * support all of them... - */ - if (spi->mode & SPI_LSB_FIRST) - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, - spi->chip_select); + if (spi->mode & SPI_READY) + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_CPOL) - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, - spi->chip_select); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + davinci_dma = &(davinci_spi->dma_channels); - if (!(spi->mode & SPI_CPHA)) - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, - spi->chip_select); + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || + (davinci_dma->eventq == SPI_NO_RESOURCE)) + spi_cfg->io_type = SPI_IO_TYPE_INTR; + else if ((davinci_dma->dma_rx_channel == -1) || + (davinci_dma->dma_tx_channel == -1)) + retval = davinci_spi_request_dma(spi); + } /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + * Validate desired clock rate */ + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); + if ((prescale < 2) || (prescale > 255)) + return -EINVAL; - if (davinci_spi->version == SPI_VERSION_2) { - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, - spi->chip_select); - set_fmt_bits(davinci_spi->base, - (davinci_spi->pdata->wdelay - << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->odd_parity) - set_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_ODD_PARITY_MASK, - spi->chip_select); - - if (davinci_spi->pdata->parity_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_PARITYENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->wait_enable) - set_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_WAITENA_MASK, - spi->chip_select); - - if (davinci_spi->pdata->timer_disable) - set_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - else - clear_fmt_bits(davinci_spi->base, - SPIFMT_DISTIMER_MASK, - spi->chip_select); - } - - retval = davinci_spi_setup_transfer(spi, NULL); + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", + io_type_names[spi_cfg->io_type]); return retval; } @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) { struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); struct davinci_spi_dma *davinci_spi_dma; + struct davinci_spi_platform_data *pdata; - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if (use_dma && davinci_spi->dma_channels) { - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - if ((davinci_spi_dma->dma_rx_channel != -1) - && (davinci_spi_dma->dma_tx_channel != -1)) { - edma_free_channel(davinci_spi_dma->dma_tx_channel); - edma_free_channel(davinci_spi_dma->dma_rx_channel); - } - } -} - -static int davinci_spi_bufs_prep(struct spi_device *spi, - struct davinci_spi *davinci_spi) -{ - int op_mode = 0; - - /* - * REVISIT unless devices disagree about SPI_LOOP or - * SPI_READY (SPI_NO_CS only allows one device!), this - * should not need to be done before each message... - * optimize for both flags staying cleared. - */ - - op_mode = SPIPC0_DIFUN_MASK - | SPIPC0_DOFUN_MASK - | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; - if (spi->mode & SPI_READY) - op_mode |= SPIPC0_SPIENA_MASK; + davinci_spi_dma = &davinci_spi->dma_channels; + pdata = davinci_spi->pdata; - iowrite32(op_mode, davinci_spi->base + SPIPC0); + if (davinci_spi_dma->dma_rx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_rx_channel); - if (spi->mode & SPI_LOOP) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_LOOPBACK_MASK); + if (davinci_spi_dma->dma_tx_channel != -1) + edma_free_channel(davinci_spi_dma->dma_tx_channel); - return 0; + if (davinci_spi_dma->dummy_param_slot != -1) + edma_free_slot(davinci_spi_dma->dummy_param_slot); } static int davinci_spi_check_error(struct davinci_spi *davinci_spi, @@ -660,355 +640,242 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, } /** - * davinci_spi_bufs - functions which will handle transfer data - * @spi: spi device on which data transfer to be done - * @t: spi transfer in which transfer info is filled + * davinci_spi_process_events - check for and handle any SPI controller events + * @davinci_spi: the controller data * - * This function will put data to be transferred into data register - * of SPI controller and then wait until the completion will be marked - * by the IRQ Handler. + * This function will check the SPIFLG register and handle any events that are + * detected there */ -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) { - struct davinci_spi *davinci_spi; - int int_status, count, ret; - u8 conv, tmp; - u32 tx_data, data1_reg_val; - u32 buf_val, flg_val; - struct davinci_spi_platform_data *pdata; - - davinci_spi = spi_master_get_devdata(spi->master); - pdata = davinci_spi->pdata; - - davinci_spi->tx = t->tx_buf; - davinci_spi->rx = t->rx_buf; - - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; - - INIT_COMPLETION(davinci_spi->done); - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Enable SPI */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - - /* Determine the command to execute READ or WRITE */ - if (t->tx_buf) { - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - - while (1) { - tx_data = davinci_spi->get_tx(davinci_spi); - - data1_reg_val &= ~(0xFFFF); - data1_reg_val |= (0xFFFF & tx_data); - - buf_val = ioread32(davinci_spi->base + SPIBUF); - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - count--; - } - while (ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - /* getting the returned byte */ - if (t->rx_buf) { - buf_val = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(buf_val, davinci_spi); - } - if (count <= 0) - break; - } - } else { - if (pdata->poll_mode) { - while (1) { - /* keeps the serial clock going */ - if ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_TXFULL_MASK) == 0) - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIBUF) & - SPIBUF_RXEMPTY_MASK) - cpu_relax(); - - flg_val = ioread32(davinci_spi->base + SPIFLG); - buf_val = ioread32(davinci_spi->base + SPIBUF); - - davinci_spi->get_rx(buf_val, davinci_spi); - - count--; - if (count <= 0) - break; - } - } else { /* Receive in Interrupt mode */ - int i; - - for (i = 0; i < davinci_spi->count; i++) { - set_io_bits(davinci_spi->base + SPIINT, - SPIINT_BITERR_INTR - | SPIINT_OVRRUN_INTR - | SPIINT_RX_INTR); - - iowrite32(data1_reg_val, - davinci_spi->base + SPIDAT1); - - while (ioread32(davinci_spi->base + SPIINT) & - SPIINT_RX_INTR) - cpu_relax(); - } - iowrite32((data1_reg_val & 0x0ffcffff), - davinci_spi->base + SPIDAT1); - } + u32 status, tx_data, rx_data, spidat1; + u8 tx_word = 0; + + status = ioread32(davinci_spi->base + SPIFLG); + + if ((davinci_spi->version != SPI_VERSION_0) && + (likely(status & SPIFLG_TX_INTR_MASK)) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; + + if (likely(status & SPIFLG_RX_INTR_MASK)) { + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; + davinci_spi->get_rx(rx_data, davinci_spi); + davinci_spi->rcount--; + if ((davinci_spi->version == SPI_VERSION_0) && + (likely(davinci_spi->wcount > 0))) + tx_word = 1; } - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); - - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + if (unlikely(status & SPIFLG_ERROR_MASK)) { + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); + return -1; + } - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (likely(tx_word)) { + spidat1 = ioread32(davinci_spi->base + SPIDAT1); + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + } - return t->len; + return 0; } -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 - -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) +/** + * davinci_spi_txrx_bufs - function which will handle transfer data + * @spi: spi device on which data transfer to be done + * @t: spi transfer in which transfer info is filled + * + * This function will put data to be transferred into data register + * of SPI controller and then wait until the completion will be marked + * by the IRQ Handler. + */ +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) { struct davinci_spi *davinci_spi; - int int_status = 0; - int count, temp_count; - u8 conv = 1; - u8 tmp; - u32 data1_reg_val; - struct davinci_spi_dma *davinci_spi_dma; - int word_len, data_type, ret; - unsigned long tx_reg, rx_reg; + int data_type, ret = 0; + u32 tx_data, spidat1; + u16 tx_buf_count = 0, rx_buf_count = 0; + struct davinci_spi_config *spi_cfg; struct davinci_spi_platform_data *pdata; + struct davinci_spi_dma *davinci_dma; struct device *sdev; + dma_addr_t tx_reg, rx_reg; + void *tx_buf, *rx_buf; + struct edmacc_param rx_param, tx_param; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; - sdev = davinci_spi->bitbang.master->dev.parent; - - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; - - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; + spi_cfg = (struct davinci_spi_config *)spi->controller_data; + davinci_dma = &(davinci_spi->dma_channels); davinci_spi->tx = t->tx_buf; davinci_spi->rx = t->rx_buf; + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; + davinci_spi->rcount = davinci_spi->wcount; + davinci_spi->errors = 0; - /* convert len to words based on bits_per_word */ - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; - davinci_spi->count = t->len / conv; + spidat1 = ioread32(davinci_spi->base + SPIDAT1); - INIT_COMPLETION(davinci_spi->done); - - init_completion(&davinci_spi_dma->dma_rx_completion); - init_completion(&davinci_spi_dma->dma_tx_completion); - - word_len = conv * 8; - - if (word_len <= 8) - data_type = DAVINCI_DMA_DATA_TYPE_S8; - else if (word_len <= 16) - data_type = DAVINCI_DMA_DATA_TYPE_S16; - else if (word_len <= 32) - data_type = DAVINCI_DMA_DATA_TYPE_S32; - else - return -EINVAL; - - ret = davinci_spi_bufs_prep(spi, davinci_spi); - if (ret) - return ret; - - /* Put delay val if required */ - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), - davinci_spi->base + SPIDELAY); - - count = davinci_spi->count; /* the number of elements */ - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; - - /* CS default = 0xFF */ - tmp = ~(0x1 << spi->chip_select); - - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); - - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; - - /* disable all interrupts for dma transfers */ - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); - /* Disable SPI to write configuration bits in SPIDAT */ - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - /* Enable SPI */ + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) - cpu_relax(); - + INIT_COMPLETION(davinci_spi->done); - if (t->tx_buf) { - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX buffer\n", count); - return -ENOMEM; + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { + + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); + + /* start the transfer */ + davinci_spi->wcount--; + tx_data = davinci_spi->get_tx(davinci_spi); + spidat1 &= 0xFFFF0000; + spidat1 |= (tx_data & 0xFFFF); + iowrite32(spidat1, davinci_spi->base + SPIDAT1); + + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + data_type = spi_cfg->bytes_per_word; + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; + + if (t->tx_buf) { + tx_buf = ((void *)t->tx_buf); + tx_buf_count = davinci_spi->wcount; + } else { + tx_buf = (void *)davinci_spi->tmp_buf; + tx_buf_count = SPI_BUFSIZ; } - temp_count = count; - } else { - /* We need TX clocking for RX transaction */ - t->tx_dma = dma_map_single(&spi->dev, - (void *)davinci_spi->tmp_buf, count + 1, - DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - dev_dbg(sdev, "Unable to DMA map a %d bytes" - " TX tmp buffer\n", count); - return -ENOMEM; + if (t->rx_buf) { + rx_buf = (void *)t->rx_buf; + rx_buf_count = davinci_spi->rcount; + } else { + rx_buf = (void *)davinci_spi->tmp_buf; + rx_buf_count = SPI_BUFSIZ; } - temp_count = count + 1; + + t->tx_dma = dma_map_single(&spi->dev, tx_buf, + tx_buf_count, DMA_TO_DEVICE); + t->rx_dma = dma_map_single(&spi->dev, rx_buf, + rx_buf_count, DMA_FROM_DEVICE); + + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; + tx_param.dst = tx_reg; + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; + tx_param.link_bcntrld = 0xffff; + tx_param.src_dst_cidx = 0; + tx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); + edma_link(davinci_dma->dma_tx_channel, + davinci_dma->dummy_param_slot); + + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); + rx_param.src = rx_reg; + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; + rx_param.dst = t->rx_dma; + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; + rx_param.link_bcntrld = 0xffff; + rx_param.src_dst_cidx = 0; + rx_param.ccnt = 1; + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); + + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, + davinci_spi->base + SPIDAT1 + 2); + + edma_start(davinci_dma->dma_rx_channel); + edma_start(davinci_dma->dma_tx_channel); + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); } - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, - data_type, temp_count, 1, 0, ASYNC); - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); - - if (t->rx_buf) { - /* initiate transaction */ - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); - - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, - DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, t->rx_dma)) { - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", - count); - if (t->tx_buf != NULL) - dma_unmap_single(NULL, t->tx_dma, - count, DMA_TO_DEVICE); - return -ENOMEM; + /* Wait for the transfer to complete */ + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { + wait_for_completion_interruptible(&(davinci_spi->done)); + } else { + while ((davinci_spi->rcount > 0) && (ret == 0)) { + ret = davinci_spi_process_events(davinci_spi); + cpu_relax(); } - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, - data_type, count, 1, 0, ASYNC); - edma_set_src(davinci_spi_dma->dma_rx_channel, - rx_reg, INCR, W8BIT); - edma_set_dest(davinci_spi_dma->dma_rx_channel, - t->rx_dma, INCR, W8BIT); - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, - data_type, 0); } - if ((t->tx_buf) || (t->rx_buf)) - edma_start(davinci_spi_dma->dma_tx_channel); - - if (t->rx_buf) - edma_start(davinci_spi_dma->dma_rx_channel); - - if ((t->rx_buf) || (t->tx_buf)) - davinci_spi_set_dma_req(spi, 1); - - if (t->tx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_tx_completion); - - if (t->rx_buf) - wait_for_completion_interruptible( - &davinci_spi_dma->dma_rx_completion); - - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); - - if (t->rx_buf) - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); - - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - int_status = ioread32(davinci_spi->base + SPIFLG); + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, + DMA_TO_DEVICE); + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, + DMA_FROM_DEVICE); + } - ret = davinci_spi_check_error(davinci_spi, int_status); - if (ret != 0) - return ret; + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* SPI Framework maintains the count only in bytes so convert back */ - davinci_spi->count *= conv; + if (davinci_spi->errors) { + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); + if (ret != 0) + return ret; + } + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { + sdev = davinci_spi->bitbang.master->dev.parent; + dev_info(sdev, "SPI data transfer error\n"); + return -EIO; + } return t->len; } /** - * davinci_spi_irq - IRQ handler for DaVinci SPI + * davinci_spi_irq - probe function for SPI Master Controller * @irq: IRQ number for this SPI Master * @context_data: structure for SPI Master controller davinci_spi + * + * ISR will determine that interrupt arrives either for READ or WRITE command. + * According to command it will do the appropriate action. It will check + * transfer length and if it is not zero then dispatch transfer command again. + * If transfer length is zero then it will indicate the COMPLETION so that + * davinci_spi_bufs function can go ahead. */ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) { struct davinci_spi *davinci_spi = context_data; - u32 int_status, rx_data = 0; - irqreturn_t ret = IRQ_NONE; + int status; - int_status = ioread32(davinci_spi->base + SPIFLG); + status = davinci_spi_process_events(davinci_spi); + if (unlikely(status != 0)) + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); - while ((int_status & SPIFLG_RX_INTR_MASK)) { - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { - ret = IRQ_HANDLED; + if ((davinci_spi->rcount == 0) || (status != 0)) + complete(&(davinci_spi->done)); - rx_data = ioread32(davinci_spi->base + SPIBUF); - davinci_spi->get_rx(rx_data, davinci_spi); + return IRQ_HANDLED; +} - /* Disable Receive Interrupt */ - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), - davinci_spi->base + SPIINT); - } else - (void)davinci_spi_check_error(davinci_spi, int_status); +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, + unsigned long index) +{ + struct resource *r; - int_status = ioread32(davinci_spi->base + SPIFLG); - } + r = platform_get_resource(dev, IORESOURCE_DMA, index); + if (r != NULL) + return r->start; - return ret; + return SPI_NO_RESOURCE; } /** * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data + * + * According to Linux Device Model this function will be invoked by Linux + * with platform_device struct which contains the device specific info. + * This function will map the SPI controller's memory, register IRQ, + * Reset SPI controller and setting its registers to default value. + * It will invoke spi_bitbang_start to create work queue so that client driver + * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) resource_size_t dma_tx_chan = SPI_NO_RESOURCE; resource_size_t dma_eventq = SPI_NO_RESOURCE; int i = 0, ret = 0; + u32 spipc0; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1071,10 +939,12 @@ static int davinci_spi_probe(struct platform_device *pdev) goto unmap_io; } - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), davinci_spi); - if (ret) + if (ret != 0) { + ret = -EAGAIN; goto unmap_io; + } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; davinci_spi->version = pdata->version; - use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; - if (use_dma) { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r) - dma_rx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r) - dma_tx_chan = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); - if (r) - dma_eventq = r->start; - } - - if (!use_dma || - dma_rx_chan == SPI_NO_RESOURCE || - dma_tx_chan == SPI_NO_RESOURCE || - dma_eventq == SPI_NO_RESOURCE) { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; - use_dma = 0; - } else { - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; - davinci_spi->dma_channels = kzalloc(master->num_chipselect - * sizeof(struct davinci_spi_dma), GFP_KERNEL); - if (davinci_spi->dma_channels == NULL) { - ret = -ENOMEM; - goto free_clk; - } - - for (i = 0; i < master->num_chipselect; i++) { - davinci_spi->dma_channels[i].dma_rx_channel = -1; - davinci_spi->dma_channels[i].dma_rx_sync_dev = - dma_rx_chan; - davinci_spi->dma_channels[i].dma_tx_channel = -1; - davinci_spi->dma_channels[i].dma_tx_sync_dev = - dma_tx_chan; - davinci_spi->dma_channels[i].eventq = dma_eventq; - } - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" - "Using RX channel = %d , TX channel = %d and " - "event queue = %d", dma_rx_chan, dma_tx_chan, - dma_eventq); - } + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); + davinci_spi->dma_channels.dma_rx_channel = -1; + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; + davinci_spi->dma_channels.dma_tx_channel = -1; + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; + davinci_spi->dma_channels.dummy_param_slot = -1; + davinci_spi->dma_channels.eventq = dma_eventq; davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; @@ -1164,31 +1002,28 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); - /* Clock internal */ - if (davinci_spi->pdata->clk_internal) - set_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); - else - clear_io_bits(davinci_spi->base + SPIGCR1, - SPIGCR1_CLKMOD_MASK); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + iowrite32(spipc0, davinci_spi->base + SPIPC0); - /* master mode default */ - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + /* initialize chip selects */ + if (pdata->chip_sel != NULL) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); - if (davinci_spi->pdata->intr_level) - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); - else - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); ret = spi_bitbang_start(&davinci_spi->bitbang); - if (ret) + if (ret != 0) goto free_clk; - dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); - - if (!pdata->poll_mode) - dev_info(&pdev->dev, "Operating in interrupt mode" - " using IRQ %d\n", davinci_spi->irq); + dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); return ret; @@ -1220,7 +1055,7 @@ err: * It will also call spi_bitbang_stop to destroy the work queue which was * created by spi_bitbang_start. */ -static int __exit davinci_spi_remove(struct platform_device *pdev) +static int __devexit davinci_spi_remove(struct platform_device *pdev) { struct davinci_spi *davinci_spi; struct spi_master *master; @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) } static struct platform_driver davinci_spi_driver = { - .driver.name = "spi_davinci", - .remove = __exit_p(davinci_spi_remove), + .driver = { + .name = "spi_davinci", + .owner = THIS_MODULE, + }, + .remove = __devexit_p(davinci_spi_remove), }; static int __init davinci_spi_init(void) -- 1.6.3.3 ------------------------------------------------------------------------------ The Palm PDK Hot Apps Program offers developers who use the Plug-In Development Kit to bring their C/C++ apps to Palm for a share of $1 Million in cash or HP Products. Visit us here for more details: http://p.sf.net/sfu/dev2dev-palm ^ permalink raw reply related [flat|nested] 33+ messages in thread
[parent not found: <1280355490-11878-2-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <1280355490-11878-2-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> @ 2010-08-01 5:12 ` Grant Likely [not found] ` <AANLkTimu+G-5wTrdQ6YiWi60i+5uN9sydfsZKMKQX7_f-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Grant Likely @ 2010-08-01 5:12 UTC (permalink / raw) To: Brian Niebuhr Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ On Wed, Jul 28, 2010 at 4:18 PM, Brian Niebuhr <bniebuhr3-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > INTRODUCTION > > I have been working on a custom OMAP-L138 board that has multiple spi > devices (seven) on one controller. These devices have a wide range of > transfer parameters (speed, phase, polarity, internal and gpio chip > selects). During my testing I found multiple errors in the davinci spi > driver as a result of this complex setup. The primary issues were: > > 1. There is a race condition due to the SPIBUF read busy-waits for slow > devices > 2. I found some DMA transfer length errors under some conditions > 3. The chip select code caused extra byte transfers (with no chip > select active) due to writes to SPIDAT1 > 4. Several issues prevented using multiple SPI devices, especially > the DMA code, as disucussed previously on the davinci list. > > The fixes to these problems were not simple. I ended up making fairly > large changes to the driver, and those changes are contained in these > patches. The full list of changes follows. > > CHANGE LIST > > 1. davinci_spi_chipelect() now performs both activation and deactivation > of chip selects. This lets spi_bitbang fully control chip > select activation, as intended by the SPI API. > 2. Chip select activation does not cause extra writes to the SPI bus > 3. Chip select activation does not use SPIDEF for control. This change > will also allow for implementation of inverted (active high) > chip selects in the future. > 4. Added back gpio chip select capability from the old driver > 5. Fixed prescale calculation for non-integer fractions of spi clock > 6. Allow specification of SPI transfer parameters on a per-device > (instead of per-controller) basis > 7. Allow specification of polled, interrupt-based, or DMA operation on > a per-device basis > 8. Allow DMA with when more than one device is connected > 9. Combined pio and dma txrx_bufs functions into one since they share > large parts of their functionality, and to simplify item (8). > 10. Use only SPIFMT0 to allow more than 4 devices > > TESTING > > I have tested the driver using a custom SPI stress test on my > OMAP-L138-based board with three devices connected. I have tested > configurations with all three devices polled, all three interrupt-based, > all three DMA, and a mixture. > > I have compiled with the davinci_all_defconfig, but I don't have EVMs > for the other davinci platforms to test with. > > Signed-off-by: Brian Niebuhr <bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> Hi Brian, I'm getting a little frustrated, and I wouldn't be surprised if you're getting a little frustrated too, but I cannot merge this as is. It is just too big to be able to review sanely, when I know there are bite-size chunks that can be factored out into separate patches and can be merged independently. At a *bare minimum* I would need acks from several davinci users that it is tested and working before I'd merge something like this, but even then I'm not sure I would. It certainly will not make me happy. It also means that when someone does have problems with the new driver over the old that they won't have a hope of bisecting it to figure out which change broken their system. There will be less pain all around if you split it up instead. ... In fact, after taking another look at it, I insist. I can tell that while major changes have been made, it is *still* the same driver with changes that can be logically identified. Split it up. I'm more than happy to help you with the tools and techniques for splitting a single monolithic patch into logical changes if you've not done that before. Send me a private email if you prefer. Comments below: > --- > arch/arm/mach-davinci/board-dm355-evm.c | 10 + > arch/arm/mach-davinci/board-dm355-leopard.c | 10 + > arch/arm/mach-davinci/board-dm365-evm.c | 10 + > arch/arm/mach-davinci/dm355.c | 8 +- > arch/arm/mach-davinci/dm365.c | 6 - > arch/arm/mach-davinci/include/mach/spi.h | 35 +- > drivers/spi/davinci_spi.c | 1098 ++++++++++++--------------- > 7 files changed, 521 insertions(+), 656 deletions(-) > > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c > index a319101..ad8779b 100644 > --- a/arch/arm/mach-davinci/board-dm355-evm.c > +++ b/arch/arm/mach-davinci/board-dm355-evm.c > @@ -32,6 +32,7 @@ > #include <mach/nand.h> > #include <mach/mmc.h> > #include <mach/usb.h> > +#include <mach/spi.h> > > /* NOTE: this is geared for the standard config, with a socketed > * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you > @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm355_evm_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640a, > + .controller_data = &at25640a_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c > index f1d8132..b2d8d48 100644 > --- a/arch/arm/mach-davinci/board-dm355-leopard.c > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c > @@ -29,6 +29,7 @@ > #include <mach/nand.h> > #include <mach/mmc.h> > #include <mach/usb.h> > +#include <mach/spi.h> > > /* NOTE: this is geared for the standard config, with a socketed > * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you > @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640a_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm355_leopard_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640a, > + .controller_data = &at25640a_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c > index 5bb86b2..db85372 100644 > --- a/arch/arm/mach-davinci/board-dm365-evm.c > +++ b/arch/arm/mach-davinci/board-dm365-evm.c > @@ -39,6 +39,7 @@ > #include <mach/mmc.h> > #include <mach/nand.h> > #include <mach/keyscan.h> > +#include <mach/spi.h> > > #include <media/tvp514x.h> > > @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { > .flags = EE_ADDR2, > }; > > +static struct davinci_spi_config at25640_spi_cfg = { > + .parity_enable = false, > + .intr_level = 0, > + .io_type = SPI_IO_TYPE_DMA, > + .wdelay = 0, > + .timer_disable = true, > +}; > + > static struct spi_board_info dm365_evm_spi_info[] __initconst = { > { > .modalias = "at25", > .platform_data = &at25640, > + .controller_data = &at25640_spi_cfg, > .max_speed_hz = 10 * 1000 * 1000, > .bus_num = 0, > .chip_select = 0, > diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c > index 3834781..b79b798 100644 > --- a/arch/arm/mach-davinci/dm355.c > +++ b/arch/arm/mach-davinci/dm355.c > @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { > }; > > static struct davinci_spi_platform_data dm355_spi0_pdata = { > - .version = SPI_VERSION_1, > + .version = SPI_VERSION_0, > .num_chipselect = 2, > - .clk_internal = 1, > - .cs_hold = 1, > - .intr_level = 0, > - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ > - .c2tdelay = 0, > - .t2cdelay = 0, > }; > static struct platform_device dm355_spi0_device = { > .name = "spi_davinci", > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c > index 652f4b6..4aea346 100644 > --- a/arch/arm/mach-davinci/dm365.c > +++ b/arch/arm/mach-davinci/dm365.c > @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); > static struct davinci_spi_platform_data dm365_spi0_pdata = { > .version = SPI_VERSION_1, > .num_chipselect = 2, > - .clk_internal = 1, > - .cs_hold = 1, > - .intr_level = 0, > - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ > - .c2tdelay = 0, > - .t2cdelay = 0, > }; > > static struct resource dm365_spi0_resources[] = { > diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h > index 910efbf..3f77dab 100644 > --- a/arch/arm/mach-davinci/include/mach/spi.h > +++ b/arch/arm/mach-davinci/include/mach/spi.h > @@ -19,26 +19,35 @@ > #ifndef __ARCH_ARM_DAVINCI_SPI_H > #define __ARCH_ARM_DAVINCI_SPI_H > > +#define SPI_INTERN_CS 0xFF > + > enum { > - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ > + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ > + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ > SPI_VERSION_2, /* For DA8xx */ > }; > > struct davinci_spi_platform_data { > u8 version; > - u8 num_chipselect; > - u8 wdelay; > - u8 odd_parity; > - u8 parity_enable; > - u8 wait_enable; > - u8 timer_disable; > - u8 clk_internal; > - u8 cs_hold; > + u16 num_chipselect; > + u8 *chip_sel; > +}; > + > +struct davinci_spi_config { > + bool odd_parity; > + bool parity_enable; > u8 intr_level; > - u8 poll_mode; > - u8 use_dma; > - u8 c2tdelay; > - u8 t2cdelay; > + u8 io_type; > +#define SPI_IO_TYPE_INTR 0 > +#define SPI_IO_TYPE_POLL 1 > +#define SPI_IO_TYPE_DMA 2 > + u8 bytes_per_word; > + u8 wdelay; > + bool timer_disable; > + u8 c2t_delay; > + u8 t2c_delay; > + u8 t2e_delay; > + u8 c2e_delay; > }; > > #endif /* __ARCH_ARM_DAVINCI_SPI_H */ > diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c > index b85090c..5c9e9ce 100644 > --- a/drivers/spi/davinci_spi.c > +++ b/drivers/spi/davinci_spi.c > @@ -1,5 +1,6 @@ > /* > * Copyright (C) 2009 Texas Instruments. > + * Copyright (C) 2010 EF Johnson Technologies > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -27,21 +28,19 @@ > #include <linux/dma-mapping.h> > #include <linux/spi/spi.h> > #include <linux/spi/spi_bitbang.h> > -#include <linux/slab.h> > > #include <mach/spi.h> > #include <mach/edma.h> > > #define SPI_NO_RESOURCE ((resource_size_t)-1) > > -#define SPI_MAX_CHIPSELECT 2 > - > #define CS_DEFAULT 0xFF > > #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) > -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 > + > +#define RX_DMA_INDEX 0 > +#define TX_DMA_INDEX 1 > +#define EVENTQ_DMA_INDEX 2 > > #define SPIFMT_PHASE_MASK BIT(16) > #define SPIFMT_POLARITY_MASK BIT(17) > @@ -53,9 +52,11 @@ > #define SPIFMT_WDELAY_MASK 0x3f000000u > #define SPIFMT_WDELAY_SHIFT 24 > #define SPIFMT_CHARLEN_MASK 0x0000001Fu > +#define SPIFMT_PRESCALE_SHIFT 8 > > /* SPIGCR1 */ > -#define SPIGCR1_SPIENA_MASK 0x01000000u > +#define SPIGCR1_SPIENA_MASK BIT(24) > +#define SPIGCR1_POWERDOWN_MASK BIT(8) > > /* SPIPC0 */ > #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ > @@ -66,20 +67,38 @@ > #define SPIPC0_EN0FUN_MASK BIT(0) > > #define SPIINT_MASKALL 0x0101035F > +#define SPIINT_MASKINT 0x0000035F > #define SPI_INTLVL_1 0x000001FFu > #define SPI_INTLVL_0 0x00000000u > > /* SPIDAT1 */ > +#define SPIDAT1_CSHOLD_MASK BIT(28) > #define SPIDAT1_CSHOLD_SHIFT 28 > +#define SPIDAT1_WDEL_MASK BIT(26) > +#define SPIDAT1_CSNR_MASK 0x00FF0000u > #define SPIDAT1_CSNR_SHIFT 16 > +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) > #define SPIGCR1_CLKMOD_MASK BIT(1) > -#define SPIGCR1_MASTER_MASK BIT(0) > +#define SPIGCR1_MASTER_MASK BIT(0) > #define SPIGCR1_LOOPBACK_MASK BIT(16) > > /* SPIBUF */ > #define SPIBUF_TXFULL_MASK BIT(29) > #define SPIBUF_RXEMPTY_MASK BIT(31) > > +/* SPIDELAY */ > +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u > +#define SPIDELAY_C2TDELAY_SHIFT 24 > +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u > +#define SPIDELAY_T2CDELAY_SHIFT 16 > +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u > +#define SPIDELAY_T2EDELAY_SHIFT 8 > +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu > +#define SPIDELAY_C2EDELAY_SHIFT 0 > + > +/* SPIDEF */ > +#define SPIDEF_CSDEF_MASK 0x000000FFu > + > /* Error Masks */ > #define SPIFLG_DLEN_ERR_MASK BIT(0) > #define SPIFLG_TIMEOUT_MASK BIT(1) > @@ -90,11 +109,12 @@ > #define SPIFLG_RX_INTR_MASK BIT(8) > #define SPIFLG_TX_INTR_MASK BIT(9) > #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) > -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ > +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ > | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ > | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ > - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ > - | SPIFLG_TX_INTR_MASK \ > + | SPIFLG_OVRRUN_MASK) > +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ > + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ > | SPIFLG_BUF_INIT_ACTIVE_MASK) > > #define SPIINT_DLEN_ERR_INTR BIT(0) > @@ -139,11 +159,10 @@ > #define TGINTVEC0 0x60 > #define TGINTVEC1 0x64 > > -struct davinci_spi_slave { > - u32 cmd_to_write; > - u32 clk_ctrl_to_write; > - u32 bytes_per_word; > - u8 active_cs; > +const char * const io_type_names[] = { > + [SPI_IO_TYPE_INTR] = "Interrupt", > + [SPI_IO_TYPE_POLL] = "Polled", > + [SPI_IO_TYPE_DMA] = "DMA", > }; > > /* We have 2 DMA channels per CS, one for RX and one for TX */ > @@ -152,10 +171,8 @@ struct davinci_spi_dma { > int dma_rx_channel; > int dma_tx_sync_dev; > int dma_rx_sync_dev; > + int dummy_param_slot; > enum dma_event_q eventq; > - > - struct completion dma_tx_completion; > - struct completion dma_rx_completion; > }; > > /* SPI Controller driver's private data. */ > @@ -173,51 +190,53 @@ struct davinci_spi { > const void *tx; > void *rx; > u8 *tmp_buf; > - int count; > - struct davinci_spi_dma *dma_channels; > - struct davinci_spi_platform_data *pdata; > + int rcount; > + int wcount; > + u32 errors; > + struct davinci_spi_dma dma_channels; > + struct davinci_spi_platform_data *pdata; > > void (*get_rx)(u32 rx_data, struct davinci_spi *); > u32 (*get_tx)(struct davinci_spi *); > - > - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; > }; > > -static unsigned use_dma; > - > static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) > { > - u8 *rx = davinci_spi->rx; > - > - *rx++ = (u8)data; > - davinci_spi->rx = rx; > + if (davinci_spi->rx) { > + u8 *rx = davinci_spi->rx; > + *rx++ = (u8)data; > + davinci_spi->rx = rx; > + } > } > > static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) > { > - u16 *rx = davinci_spi->rx; > - > - *rx++ = (u16)data; > - davinci_spi->rx = rx; > + if (davinci_spi->rx) { > + u16 *rx = davinci_spi->rx; > + *rx++ = (u16)data; > + davinci_spi->rx = rx; > + } > } > > static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) > { > - u32 data; > - const u8 *tx = davinci_spi->tx; > - > - data = *tx++; > - davinci_spi->tx = tx; > + u32 data = 0; > + if (davinci_spi->tx) { > + const u8 *tx = davinci_spi->tx; > + data = *tx++; > + davinci_spi->tx = tx; > + } > return data; > } Here's an excellent candidate for a separate patch. Validation of the rx/tx buffer before transfering data to/from it. > > static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) > { > - u32 data; > - const u16 *tx = davinci_spi->tx; > - > - data = *tx++; > - davinci_spi->tx = tx; > + u32 data = 0; > + if (davinci_spi->tx) { > + const u16 *tx = davinci_spi->tx; > + data = *tx++; > + davinci_spi->tx = tx; > + } > return data; > } > > @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) > iowrite32(v, addr); > } > > -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) > -{ > - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); > -} > - > -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) > -{ > - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > - > - if (enable) > - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > - else > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > -} > - > /* > * Interface to control the chip select signal > */ > @@ -264,25 +263,54 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > { > struct davinci_spi *davinci_spi; > struct davinci_spi_platform_data *pdata; > - u32 data1_reg_val = 0; > + u8 i, chip_sel = spi->chip_select; > + u32 spidat1; > + u16 spidat1_cfg; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > > - /* > - * Board specific chip select logic decides the polarity and cs > - * line for the controller > - */ > - if (value == BITBANG_CS_INACTIVE) { > - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); > - > - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > + spidat1 = SPIDAT1_CSNR_MASK; > + if (value == BITBANG_CS_ACTIVE) > + spidat1 |= SPIDAT1_CSHOLD_MASK; > + else > + spidat1 |= SPIDAT1_WDEL_MASK; > > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > + if (pdata->chip_sel == NULL) { > + if (value == BITBANG_CS_ACTIVE) > + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); > + } else { > + for (i = 0; i < pdata->num_chipselect; i++) { > + if (pdata->chip_sel[i] == SPI_INTERN_CS) { > + if ((i == chip_sel) && > + (value == BITBANG_CS_ACTIVE)) { > + spidat1 &= ~((0x1 << chip_sel) > + << SPIDAT1_CSNR_SHIFT); > + } > + } else { > + if (value == BITBANG_CS_INACTIVE) > + gpio_set_value(pdata->chip_sel[i], 1); > + else if (i == chip_sel) > + gpio_set_value(pdata->chip_sel[i], 0); > + } > + } > } > + > + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; > + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); > +} > + > +/** > + * davinci_spi_get_prescale - Calculates the correct prescale value > + * @max_speed_hz: the maximum rate the SPI clock can run at > + * > + * This function calculates the prescale value that generates a clock rate > + * less than or equal to the specified maximum > + */ > +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, > + u32 max_speed_hz) > +{ > + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; > } > > /** > @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) > static int davinci_spi_setup_transfer(struct spi_device *spi, > struct spi_transfer *t) > { > - > struct davinci_spi *davinci_spi; > struct davinci_spi_platform_data *pdata; > + struct davinci_spi_config *spi_cfg; > u8 bits_per_word = 0; > - u32 hz = 0, prescale = 0, clkspeed; > + u32 hz = 0, spifmt = 0, prescale, delay = 0; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > + spi_cfg = spi->controller_data; > > if (t) { > bits_per_word = t->bits_per_word; > @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, > if (bits_per_word <= 8 && bits_per_word >= 2) { > davinci_spi->get_rx = davinci_spi_rx_buf_u8; > davinci_spi->get_tx = davinci_spi_tx_buf_u8; > - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; > + spi_cfg->bytes_per_word = 1; > } else if (bits_per_word <= 16 && bits_per_word >= 2) { > davinci_spi->get_rx = davinci_spi_rx_buf_u16; > davinci_spi->get_tx = davinci_spi_tx_buf_u16; > - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; > + spi_cfg->bytes_per_word = 2; > } else > return -EINVAL; > > if (!hz) > hz = spi->max_speed_hz; > > - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, > - spi->chip_select); > - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, > - spi->chip_select); > + prescale = davinci_spi_get_prescale(davinci_spi, hz); > + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); > + > + spifmt |= (bits_per_word & 0x1f); > + > + if (spi->mode & SPI_LSB_FIRST) > + spifmt |= SPIFMT_SHIFTDIR_MASK; > + > + if (spi->mode & SPI_CPOL) > + spifmt |= SPIFMT_POLARITY_MASK; > + > + if (!(spi->mode & SPI_CPHA)) > + spifmt |= SPIFMT_PHASE_MASK; > + > + if (davinci_spi->version == SPI_VERSION_2) { > + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) > + & SPIFMT_WDELAY_MASK); > + > + if (spi_cfg->odd_parity) > + spifmt |= SPIFMT_ODD_PARITY_MASK; > + > + if (spi_cfg->parity_enable) > + spifmt |= SPIFMT_PARITYENA_MASK; > + > + if (spi->mode & SPI_READY) { > + spifmt |= SPIFMT_WAITENA_MASK; > + delay |= (spi_cfg->t2e_delay > + << SPIDELAY_T2EDELAY_SHIFT) > + & SPIDELAY_T2EDELAY_MASK; > + delay |= (spi_cfg->c2e_delay > + << SPIDELAY_C2EDELAY_SHIFT) > + & SPIDELAY_C2EDELAY_MASK; > + } > + > + if (spi_cfg->timer_disable) { > + spifmt |= SPIFMT_DISTIMER_MASK; > + } else { > + delay |= (spi_cfg->c2t_delay > + << SPIDELAY_C2TDELAY_SHIFT) > + & SPIDELAY_C2TDELAY_MASK; > + delay |= (spi_cfg->t2c_delay > + << SPIDELAY_T2CDELAY_SHIFT) > + & SPIDELAY_T2CDELAY_MASK; > + } > > - clkspeed = clk_get_rate(davinci_spi->clk); > - if (hz > clkspeed / 2) > - prescale = 1 << 8; > - if (hz < clkspeed / 256) > - prescale = 255 << 8; > - if (!prescale) > - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; > + iowrite32(delay, davinci_spi->base + SPIDELAY); > + } > + > + iowrite32(spifmt, davinci_spi->base + SPIFMT0); > > - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); > - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); > + if (spi_cfg->intr_level) > + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > + else > + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + > + if (spi->mode & SPI_LOOP) > + set_io_bits(davinci_spi->base + SPIGCR1, > + SPIGCR1_LOOPBACK_MASK); > + else > + clear_io_bits(davinci_spi->base + SPIGCR1, > + SPIGCR1_LOOPBACK_MASK); > > return 0; > } > > static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) > { > - struct spi_device *spi = (struct spi_device *)data; > - struct davinci_spi *davinci_spi; > + struct davinci_spi *davinci_spi = data; > struct davinci_spi_dma *davinci_spi_dma; > struct davinci_spi_platform_data *pdata; > > - davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + davinci_spi_dma = &(davinci_spi->dma_channels); > pdata = davinci_spi->pdata; > > + edma_stop(davinci_spi_dma->dma_rx_channel); > + > if (ch_status == DMA_COMPLETE) > - edma_stop(davinci_spi_dma->dma_rx_channel); > - else > - edma_clean_channel(davinci_spi_dma->dma_rx_channel); > + davinci_spi->rcount = 0; > > - complete(&davinci_spi_dma->dma_rx_completion); > - /* We must disable the DMA RX request */ > - davinci_spi_set_dma_req(spi, 0); > + complete(&davinci_spi->done); > } > > static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) > { > - struct spi_device *spi = (struct spi_device *)data; > - struct davinci_spi *davinci_spi; > + struct davinci_spi *davinci_spi = data; > struct davinci_spi_dma *davinci_spi_dma; > struct davinci_spi_platform_data *pdata; > > - davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); > + davinci_spi_dma = &(davinci_spi->dma_channels); > pdata = davinci_spi->pdata; > > - if (ch_status == DMA_COMPLETE) > - edma_stop(davinci_spi_dma->dma_tx_channel); > - else > - edma_clean_channel(davinci_spi_dma->dma_tx_channel); > + edma_stop(davinci_spi_dma->dma_tx_channel); > > - complete(&davinci_spi_dma->dma_tx_completion); > - /* We must disable the DMA TX request */ > - davinci_spi_set_dma_req(spi, 0); > + if (ch_status == DMA_COMPLETE) > + davinci_spi->wcount = 0; > } > > static int davinci_spi_request_dma(struct spi_device *spi) > @@ -403,30 +468,51 @@ static int davinci_spi_request_dma(struct spi_device *spi) > int r; > > davinci_spi = spi_master_get_devdata(spi->master); > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > + davinci_spi_dma = &davinci_spi->dma_channels; > pdata = davinci_spi->pdata; > sdev = davinci_spi->bitbang.master->dev.parent; > > r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, > - davinci_spi_dma_rx_callback, spi, > + davinci_spi_dma_rx_callback, davinci_spi, > davinci_spi_dma->eventq); > if (r < 0) { > - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); > - return -EAGAIN; > + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); > + r = -EAGAIN; > + goto rx_dma_failed; > } > davinci_spi_dma->dma_rx_channel = r; > + > r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, > - davinci_spi_dma_tx_callback, spi, > + davinci_spi_dma_tx_callback, davinci_spi, > davinci_spi_dma->eventq); > if (r < 0) { > - edma_free_channel(davinci_spi_dma->dma_rx_channel); > - davinci_spi_dma->dma_rx_channel = -1; > - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); > - return -EAGAIN; > + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); > + r = -EAGAIN; > + goto tx_dma_failed; > } > davinci_spi_dma->dma_tx_channel = r; > > + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), > + EDMA_SLOT_ANY); > + if (r < 0) { > + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); > + r = -EAGAIN; > + goto param_failed; > + } > + davinci_spi_dma->dummy_param_slot = r; > + edma_link(davinci_spi_dma->dummy_param_slot, > + davinci_spi_dma->dummy_param_slot); > + > return 0; > + > +param_failed: > + edma_free_channel(davinci_spi_dma->dma_tx_channel); > + davinci_spi_dma->dma_tx_channel = -1; > +tx_dma_failed: > + edma_free_channel(davinci_spi_dma->dma_rx_channel); > + davinci_spi_dma->dma_rx_channel = -1; > +rx_dma_failed: > + return r; > } > > /** > @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) > > static int davinci_spi_setup(struct spi_device *spi) > { > - int retval; > + int retval = 0; > struct davinci_spi *davinci_spi; > - struct davinci_spi_dma *davinci_spi_dma; > - struct device *sdev; > + struct davinci_spi_dma *davinci_dma; > + struct davinci_spi_platform_data *pdata; > + struct davinci_spi_config *spi_cfg; > + u32 prescale; > > davinci_spi = spi_master_get_devdata(spi->master); > - sdev = davinci_spi->bitbang.master->dev.parent; > + pdata = davinci_spi->pdata; > + spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + davinci_dma = &(davinci_spi->dma_channels); > > /* if bits per word length is zero then set it default 8 */ > if (!spi->bits_per_word) > spi->bits_per_word = 8; > > - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; > + if (!(spi->mode & SPI_NO_CS)) { > + if ((pdata->chip_sel == NULL) || > + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) > + set_io_bits(davinci_spi->base + SPIPC0, > + 1 << spi->chip_select); > > - if (use_dma && davinci_spi->dma_channels) { > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if ((davinci_spi_dma->dma_rx_channel == -1) > - || (davinci_spi_dma->dma_tx_channel == -1)) { > - retval = davinci_spi_request_dma(spi); > - if (retval < 0) > - return retval; > - } > - } > - > - /* > - * SPI in DaVinci and DA8xx operate between > - * 600 KHz and 50 MHz > - */ > - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { > - dev_dbg(sdev, "Operating frequency is not in acceptable " > - "range\n"); > - return -EINVAL; > } > > - /* > - * Set up SPIFMTn register, unique to this chipselect. > - * > - * NOTE: we could do all of these with one write. Also, some > - * of the "version 2" features are found in chips that don't > - * support all of them... > - */ > - if (spi->mode & SPI_LSB_FIRST) > - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, > - spi->chip_select); > + if (spi->mode & SPI_READY) > + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); > > - if (spi->mode & SPI_CPOL) > - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, > - spi->chip_select); > + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + davinci_dma = &(davinci_spi->dma_channels); > > - if (!(spi->mode & SPI_CPHA)) > - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, > - spi->chip_select); > + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || > + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || > + (davinci_dma->eventq == SPI_NO_RESOURCE)) > + spi_cfg->io_type = SPI_IO_TYPE_INTR; > + else if ((davinci_dma->dma_rx_channel == -1) || > + (davinci_dma->dma_tx_channel == -1)) > + retval = davinci_spi_request_dma(spi); > + } > > /* > - * Version 1 hardware supports two basic SPI modes: > - * - Standard SPI mode uses 4 pins, with chipselect > - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) > - * (distinct from SPI_3WIRE, with just one data wire; > - * or similar variants without MOSI or without MISO) > - * > - * Version 2 hardware supports an optional handshaking signal, > - * so it can support two more modes: > - * - 5 pin SPI variant is standard SPI plus SPI_READY > - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) > + * Validate desired clock rate > */ > + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); > + if ((prescale < 2) || (prescale > 255)) > + return -EINVAL; > > - if (davinci_spi->version == SPI_VERSION_2) { > - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, > - spi->chip_select); > - set_fmt_bits(davinci_spi->base, > - (davinci_spi->pdata->wdelay > - << SPIFMT_WDELAY_SHIFT) > - & SPIFMT_WDELAY_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->odd_parity) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_ODD_PARITY_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_ODD_PARITY_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->parity_enable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_PARITYENA_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_PARITYENA_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->wait_enable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_WAITENA_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_WAITENA_MASK, > - spi->chip_select); > - > - if (davinci_spi->pdata->timer_disable) > - set_fmt_bits(davinci_spi->base, > - SPIFMT_DISTIMER_MASK, > - spi->chip_select); > - else > - clear_fmt_bits(davinci_spi->base, > - SPIFMT_DISTIMER_MASK, > - spi->chip_select); > - } > - > - retval = davinci_spi_setup_transfer(spi, NULL); > + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", > + io_type_names[spi_cfg->io_type]); > > return retval; > } > @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) > { > struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); > struct davinci_spi_dma *davinci_spi_dma; > + struct davinci_spi_platform_data *pdata; > > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if (use_dma && davinci_spi->dma_channels) { > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - if ((davinci_spi_dma->dma_rx_channel != -1) > - && (davinci_spi_dma->dma_tx_channel != -1)) { > - edma_free_channel(davinci_spi_dma->dma_tx_channel); > - edma_free_channel(davinci_spi_dma->dma_rx_channel); > - } > - } > -} > - > -static int davinci_spi_bufs_prep(struct spi_device *spi, > - struct davinci_spi *davinci_spi) > -{ > - int op_mode = 0; > - > - /* > - * REVISIT unless devices disagree about SPI_LOOP or > - * SPI_READY (SPI_NO_CS only allows one device!), this > - * should not need to be done before each message... > - * optimize for both flags staying cleared. > - */ > - > - op_mode = SPIPC0_DIFUN_MASK > - | SPIPC0_DOFUN_MASK > - | SPIPC0_CLKFUN_MASK; > - if (!(spi->mode & SPI_NO_CS)) > - op_mode |= 1 << spi->chip_select; > - if (spi->mode & SPI_READY) > - op_mode |= SPIPC0_SPIENA_MASK; > + davinci_spi_dma = &davinci_spi->dma_channels; > + pdata = davinci_spi->pdata; > > - iowrite32(op_mode, davinci_spi->base + SPIPC0); > + if (davinci_spi_dma->dma_rx_channel != -1) > + edma_free_channel(davinci_spi_dma->dma_rx_channel); > > - if (spi->mode & SPI_LOOP) > - set_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_LOOPBACK_MASK); > - else > - clear_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_LOOPBACK_MASK); > + if (davinci_spi_dma->dma_tx_channel != -1) > + edma_free_channel(davinci_spi_dma->dma_tx_channel); > > - return 0; > + if (davinci_spi_dma->dummy_param_slot != -1) > + edma_free_slot(davinci_spi_dma->dummy_param_slot); > } > > static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > @@ -660,355 +640,242 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, > } > > /** > - * davinci_spi_bufs - functions which will handle transfer data > - * @spi: spi device on which data transfer to be done > - * @t: spi transfer in which transfer info is filled > + * davinci_spi_process_events - check for and handle any SPI controller events > + * @davinci_spi: the controller data > * > - * This function will put data to be transferred into data register > - * of SPI controller and then wait until the completion will be marked > - * by the IRQ Handler. > + * This function will check the SPIFLG register and handle any events that are > + * detected there > */ > -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) > +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) > { > - struct davinci_spi *davinci_spi; > - int int_status, count, ret; > - u8 conv, tmp; > - u32 tx_data, data1_reg_val; > - u32 buf_val, flg_val; > - struct davinci_spi_platform_data *pdata; > - > - davinci_spi = spi_master_get_devdata(spi->master); > - pdata = davinci_spi->pdata; > - > - davinci_spi->tx = t->tx_buf; > - davinci_spi->rx = t->rx_buf; > - > - /* convert len to words based on bits_per_word */ > - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - davinci_spi->count = t->len / conv; > - > - INIT_COMPLETION(davinci_spi->done); > - > - ret = davinci_spi_bufs_prep(spi, davinci_spi); > - if (ret) > - return ret; > - > - /* Enable SPI */ > - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - > - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - davinci_spi->base + SPIDELAY); > - > - count = davinci_spi->count; > - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > - tmp = ~(0x1 << spi->chip_select); > - > - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > - > - /* Determine the command to execute READ or WRITE */ > - if (t->tx_buf) { > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - > - while (1) { > - tx_data = davinci_spi->get_tx(davinci_spi); > - > - data1_reg_val &= ~(0xFFFF); > - data1_reg_val |= (0xFFFF & tx_data); > - > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - count--; > - } > - while (ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) > - cpu_relax(); > - > - /* getting the returned byte */ > - if (t->rx_buf) { > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - davinci_spi->get_rx(buf_val, davinci_spi); > - } > - if (count <= 0) > - break; > - } > - } else { > - if (pdata->poll_mode) { > - while (1) { > - /* keeps the serial clock going */ > - if ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_TXFULL_MASK) == 0) > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - while (ioread32(davinci_spi->base + SPIBUF) & > - SPIBUF_RXEMPTY_MASK) > - cpu_relax(); > - > - flg_val = ioread32(davinci_spi->base + SPIFLG); > - buf_val = ioread32(davinci_spi->base + SPIBUF); > - > - davinci_spi->get_rx(buf_val, davinci_spi); > - > - count--; > - if (count <= 0) > - break; > - } > - } else { /* Receive in Interrupt mode */ > - int i; > - > - for (i = 0; i < davinci_spi->count; i++) { > - set_io_bits(davinci_spi->base + SPIINT, > - SPIINT_BITERR_INTR > - | SPIINT_OVRRUN_INTR > - | SPIINT_RX_INTR); > - > - iowrite32(data1_reg_val, > - davinci_spi->base + SPIDAT1); > - > - while (ioread32(davinci_spi->base + SPIINT) & > - SPIINT_RX_INTR) > - cpu_relax(); > - } > - iowrite32((data1_reg_val & 0x0ffcffff), > - davinci_spi->base + SPIDAT1); > - } > + u32 status, tx_data, rx_data, spidat1; > + u8 tx_word = 0; > + > + status = ioread32(davinci_spi->base + SPIFLG); > + > + if ((davinci_spi->version != SPI_VERSION_0) && > + (likely(status & SPIFLG_TX_INTR_MASK)) && > + (likely(davinci_spi->wcount > 0))) > + tx_word = 1; > + > + if (likely(status & SPIFLG_RX_INTR_MASK)) { > + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; > + davinci_spi->get_rx(rx_data, davinci_spi); > + davinci_spi->rcount--; > + if ((davinci_spi->version == SPI_VERSION_0) && > + (likely(davinci_spi->wcount > 0))) > + tx_word = 1; > } > > - /* > - * Check for bit error, desync error,parity error,timeout error and > - * receive overflow errors > - */ > - int_status = ioread32(davinci_spi->base + SPIFLG); > - > - ret = davinci_spi_check_error(davinci_spi, int_status); > - if (ret != 0) > - return ret; > + if (unlikely(status & SPIFLG_ERROR_MASK)) { > + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); > + return -1; > + } > > - /* SPI Framework maintains the count only in bytes so convert back */ > - davinci_spi->count *= conv; > + if (likely(tx_word)) { > + spidat1 = ioread32(davinci_spi->base + SPIDAT1); > + davinci_spi->wcount--; > + tx_data = davinci_spi->get_tx(davinci_spi); > + spidat1 &= 0xFFFF0000; > + spidat1 |= (tx_data & 0xFFFF); > + iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + } > > - return t->len; > + return 0; > } > > -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 > -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 > -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 > - > -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) > +/** > + * davinci_spi_txrx_bufs - function which will handle transfer data > + * @spi: spi device on which data transfer to be done > + * @t: spi transfer in which transfer info is filled > + * > + * This function will put data to be transferred into data register > + * of SPI controller and then wait until the completion will be marked > + * by the IRQ Handler. > + */ > +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) > { > struct davinci_spi *davinci_spi; > - int int_status = 0; > - int count, temp_count; > - u8 conv = 1; > - u8 tmp; > - u32 data1_reg_val; > - struct davinci_spi_dma *davinci_spi_dma; > - int word_len, data_type, ret; > - unsigned long tx_reg, rx_reg; > + int data_type, ret = 0; > + u32 tx_data, spidat1; > + u16 tx_buf_count = 0, rx_buf_count = 0; > + struct davinci_spi_config *spi_cfg; > struct davinci_spi_platform_data *pdata; > + struct davinci_spi_dma *davinci_dma; > struct device *sdev; > + dma_addr_t tx_reg, rx_reg; > + void *tx_buf, *rx_buf; > + struct edmacc_param rx_param, tx_param; > > davinci_spi = spi_master_get_devdata(spi->master); > pdata = davinci_spi->pdata; > - sdev = davinci_spi->bitbang.master->dev.parent; > - > - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; > - > - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; > - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; > + spi_cfg = (struct davinci_spi_config *)spi->controller_data; > + davinci_dma = &(davinci_spi->dma_channels); > > davinci_spi->tx = t->tx_buf; > davinci_spi->rx = t->rx_buf; > + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; > + davinci_spi->rcount = davinci_spi->wcount; > + davinci_spi->errors = 0; > > - /* convert len to words based on bits_per_word */ > - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; > - davinci_spi->count = t->len / conv; > + spidat1 = ioread32(davinci_spi->base + SPIDAT1); > > - INIT_COMPLETION(davinci_spi->done); > - > - init_completion(&davinci_spi_dma->dma_rx_completion); > - init_completion(&davinci_spi_dma->dma_tx_completion); > - > - word_len = conv * 8; > - > - if (word_len <= 8) > - data_type = DAVINCI_DMA_DATA_TYPE_S8; > - else if (word_len <= 16) > - data_type = DAVINCI_DMA_DATA_TYPE_S16; > - else if (word_len <= 32) > - data_type = DAVINCI_DMA_DATA_TYPE_S32; > - else > - return -EINVAL; > - > - ret = davinci_spi_bufs_prep(spi, davinci_spi); > - if (ret) > - return ret; > - > - /* Put delay val if required */ > - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | > - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), > - davinci_spi->base + SPIDELAY); > - > - count = davinci_spi->count; /* the number of elements */ > - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; > - > - /* CS default = 0xFF */ > - tmp = ~(0x1 << spi->chip_select); > - > - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); > - > - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; > - > - /* disable all interrupts for dma transfers */ > - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > - /* Disable SPI to write configuration bits in SPIDAT */ > - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - /* Enable SPI */ > + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > > - while ((ioread32(davinci_spi->base + SPIBUF) > - & SPIBUF_RXEMPTY_MASK) == 0) > - cpu_relax(); > - > + INIT_COMPLETION(davinci_spi->done); > > - if (t->tx_buf) { > - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, > - DMA_TO_DEVICE); > - if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - dev_dbg(sdev, "Unable to DMA map a %d bytes" > - " TX buffer\n", count); > - return -ENOMEM; > + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || > + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { > + > + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) > + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > + > + /* start the transfer */ > + davinci_spi->wcount--; > + tx_data = davinci_spi->get_tx(davinci_spi); > + spidat1 &= 0xFFFF0000; > + spidat1 |= (tx_data & 0xFFFF); > + iowrite32(spidat1, davinci_spi->base + SPIDAT1); > + > + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + data_type = spi_cfg->bytes_per_word; > + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; > + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; > + > + if (t->tx_buf) { > + tx_buf = ((void *)t->tx_buf); > + tx_buf_count = davinci_spi->wcount; > + } else { > + tx_buf = (void *)davinci_spi->tmp_buf; > + tx_buf_count = SPI_BUFSIZ; > } > - temp_count = count; > - } else { > - /* We need TX clocking for RX transaction */ > - t->tx_dma = dma_map_single(&spi->dev, > - (void *)davinci_spi->tmp_buf, count + 1, > - DMA_TO_DEVICE); > - if (dma_mapping_error(&spi->dev, t->tx_dma)) { > - dev_dbg(sdev, "Unable to DMA map a %d bytes" > - " TX tmp buffer\n", count); > - return -ENOMEM; > + if (t->rx_buf) { > + rx_buf = (void *)t->rx_buf; > + rx_buf_count = davinci_spi->rcount; > + } else { > + rx_buf = (void *)davinci_spi->tmp_buf; > + rx_buf_count = SPI_BUFSIZ; > } > - temp_count = count + 1; > + > + t->tx_dma = dma_map_single(&spi->dev, tx_buf, > + tx_buf_count, DMA_TO_DEVICE); > + t->rx_dma = dma_map_single(&spi->dev, rx_buf, > + rx_buf_count, DMA_FROM_DEVICE); > + > + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); > + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; > + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; > + tx_param.dst = tx_reg; > + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; > + tx_param.link_bcntrld = 0xffff; > + tx_param.src_dst_cidx = 0; > + tx_param.ccnt = 1; > + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); > + edma_link(davinci_dma->dma_tx_channel, > + davinci_dma->dummy_param_slot); > + > + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); > + rx_param.src = rx_reg; > + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; > + rx_param.dst = t->rx_dma; > + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; > + rx_param.link_bcntrld = 0xffff; > + rx_param.src_dst_cidx = 0; > + rx_param.ccnt = 1; > + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); > + > + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, > + davinci_spi->base + SPIDAT1 + 2); > + > + edma_start(davinci_dma->dma_rx_channel); > + edma_start(davinci_dma->dma_tx_channel); > + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); > } > > - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, > - data_type, temp_count, 1, 0, ASYNC); > - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); > - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); > - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); > - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); > - > - if (t->rx_buf) { > - /* initiate transaction */ > - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); > - > - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, > - DMA_FROM_DEVICE); > - if (dma_mapping_error(&spi->dev, t->rx_dma)) { > - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", > - count); > - if (t->tx_buf != NULL) > - dma_unmap_single(NULL, t->tx_dma, > - count, DMA_TO_DEVICE); > - return -ENOMEM; > + /* Wait for the transfer to complete */ > + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { > + wait_for_completion_interruptible(&(davinci_spi->done)); > + } else { > + while ((davinci_spi->rcount > 0) && (ret == 0)) { > + ret = davinci_spi_process_events(davinci_spi); > + cpu_relax(); > } > - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, > - data_type, count, 1, 0, ASYNC); > - edma_set_src(davinci_spi_dma->dma_rx_channel, > - rx_reg, INCR, W8BIT); > - edma_set_dest(davinci_spi_dma->dma_rx_channel, > - t->rx_dma, INCR, W8BIT); > - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); > - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, > - data_type, 0); > } > > - if ((t->tx_buf) || (t->rx_buf)) > - edma_start(davinci_spi_dma->dma_tx_channel); > - > - if (t->rx_buf) > - edma_start(davinci_spi_dma->dma_rx_channel); > - > - if ((t->rx_buf) || (t->tx_buf)) > - davinci_spi_set_dma_req(spi, 1); > - > - if (t->tx_buf) > - wait_for_completion_interruptible( > - &davinci_spi_dma->dma_tx_completion); > - > - if (t->rx_buf) > - wait_for_completion_interruptible( > - &davinci_spi_dma->dma_rx_completion); > - > - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); > - > - if (t->rx_buf) > - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); > - > - /* > - * Check for bit error, desync error,parity error,timeout error and > - * receive overflow errors > - */ > - int_status = ioread32(davinci_spi->base + SPIFLG); > + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); > + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { > + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, > + DMA_TO_DEVICE); > + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, > + DMA_FROM_DEVICE); > + } > > - ret = davinci_spi_check_error(davinci_spi, int_status); > - if (ret != 0) > - return ret; > + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > - /* SPI Framework maintains the count only in bytes so convert back */ > - davinci_spi->count *= conv; > + if (davinci_spi->errors) { > + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); > + if (ret != 0) > + return ret; > + } > + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { > + sdev = davinci_spi->bitbang.master->dev.parent; > + dev_info(sdev, "SPI data transfer error\n"); > + return -EIO; > + } > > return t->len; > } > > /** > - * davinci_spi_irq - IRQ handler for DaVinci SPI > + * davinci_spi_irq - probe function for SPI Master Controller This doesn't look right. > * @irq: IRQ number for this SPI Master > * @context_data: structure for SPI Master controller davinci_spi > + * > + * ISR will determine that interrupt arrives either for READ or WRITE command. > + * According to command it will do the appropriate action. It will check > + * transfer length and if it is not zero then dispatch transfer command again. > + * If transfer length is zero then it will indicate the COMPLETION so that > + * davinci_spi_bufs function can go ahead. > */ > static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) > { > struct davinci_spi *davinci_spi = context_data; > - u32 int_status, rx_data = 0; > - irqreturn_t ret = IRQ_NONE; > + int status; > > - int_status = ioread32(davinci_spi->base + SPIFLG); > + status = davinci_spi_process_events(davinci_spi); > + if (unlikely(status != 0)) > + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); > > - while ((int_status & SPIFLG_RX_INTR_MASK)) { > - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { > - ret = IRQ_HANDLED; > + if ((davinci_spi->rcount == 0) || (status != 0)) > + complete(&(davinci_spi->done)); > > - rx_data = ioread32(davinci_spi->base + SPIBUF); > - davinci_spi->get_rx(rx_data, davinci_spi); > + return IRQ_HANDLED; > +} > > - /* Disable Receive Interrupt */ > - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), > - davinci_spi->base + SPIINT); > - } else > - (void)davinci_spi_check_error(davinci_spi, int_status); > +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, > + unsigned long index) > +{ > + struct resource *r; > > - int_status = ioread32(davinci_spi->base + SPIFLG); > - } > + r = platform_get_resource(dev, IORESOURCE_DMA, index); > + if (r != NULL) > + return r->start; > > - return ret; > + return SPI_NO_RESOURCE; > } > > /** > * davinci_spi_probe - probe function for SPI Master Controller > * @pdev: platform_device structure which contains plateform specific data > + * > + * According to Linux Device Model this function will be invoked by Linux > + * with platform_device struct which contains the device specific info. > + * This function will map the SPI controller's memory, register IRQ, > + * Reset SPI controller and setting its registers to default value. > + * It will invoke spi_bitbang_start to create work queue so that client driver > + * can register transfer method to work queue. Another candidate; improve documentation > */ > static int davinci_spi_probe(struct platform_device *pdev) > { > @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) > resource_size_t dma_tx_chan = SPI_NO_RESOURCE; > resource_size_t dma_eventq = SPI_NO_RESOURCE; > int i = 0, ret = 0; > + u32 spipc0; > > pdata = pdev->dev.platform_data; > if (pdata == NULL) { > @@ -1071,10 +939,12 @@ static int davinci_spi_probe(struct platform_device *pdev) > goto unmap_io; > } > > - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, > + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, > dev_name(&pdev->dev), davinci_spi); > - if (ret) > + if (ret != 0) { > + ret = -EAGAIN; > goto unmap_io; > + } > > /* Allocate tmp_buf for tx_buf */ > davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); > @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) > > davinci_spi->bitbang.chipselect = davinci_spi_chipselect; > davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; > + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; > > davinci_spi->version = pdata->version; > - use_dma = pdata->use_dma; > > davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; > if (davinci_spi->version == SPI_VERSION_2) > davinci_spi->bitbang.flags |= SPI_READY; > > - if (use_dma) { > - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); > - if (r) > - dma_rx_chan = r->start; > - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); > - if (r) > - dma_tx_chan = r->start; > - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); > - if (r) > - dma_eventq = r->start; > - } > - > - if (!use_dma || > - dma_rx_chan == SPI_NO_RESOURCE || > - dma_tx_chan == SPI_NO_RESOURCE || > - dma_eventq == SPI_NO_RESOURCE) { > - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; > - use_dma = 0; > - } else { > - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; > - davinci_spi->dma_channels = kzalloc(master->num_chipselect > - * sizeof(struct davinci_spi_dma), GFP_KERNEL); > - if (davinci_spi->dma_channels == NULL) { > - ret = -ENOMEM; > - goto free_clk; > - } > - > - for (i = 0; i < master->num_chipselect; i++) { > - davinci_spi->dma_channels[i].dma_rx_channel = -1; > - davinci_spi->dma_channels[i].dma_rx_sync_dev = > - dma_rx_chan; > - davinci_spi->dma_channels[i].dma_tx_channel = -1; > - davinci_spi->dma_channels[i].dma_tx_sync_dev = > - dma_tx_chan; > - davinci_spi->dma_channels[i].eventq = dma_eventq; > - } > - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" > - "Using RX channel = %d , TX channel = %d and " > - "event queue = %d", dma_rx_chan, dma_tx_chan, > - dma_eventq); > - } > + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); > + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); > + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); > + davinci_spi->dma_channels.dma_rx_channel = -1; > + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; > + davinci_spi->dma_channels.dma_tx_channel = -1; > + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; > + davinci_spi->dma_channels.dummy_param_slot = -1; > + davinci_spi->dma_channels.eventq = dma_eventq; > > davinci_spi->get_rx = davinci_spi_rx_buf_u8; > davinci_spi->get_tx = davinci_spi_tx_buf_u8; > @@ -1164,31 +1002,28 @@ static int davinci_spi_probe(struct platform_device *pdev) > udelay(100); > iowrite32(1, davinci_spi->base + SPIGCR0); > > - /* Clock internal */ > - if (davinci_spi->pdata->clk_internal) > - set_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_CLKMOD_MASK); > - else > - clear_io_bits(davinci_spi->base + SPIGCR1, > - SPIGCR1_CLKMOD_MASK); > + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ > + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; > + iowrite32(spipc0, davinci_spi->base + SPIPC0); > > - /* master mode default */ > - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + /* initialize chip selects */ > + if (pdata->chip_sel != NULL) { > + for (i = 0; i < pdata->num_chipselect; i++) { > + if (pdata->chip_sel[i] != SPI_INTERN_CS) > + gpio_direction_output(pdata->chip_sel[i], 1); > + } > + } > + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); > > - if (davinci_spi->pdata->intr_level) > - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); > - else > - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); > + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); > > ret = spi_bitbang_start(&davinci_spi->bitbang); > - if (ret) > + if (ret != 0) > goto free_clk; > > - dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); > - > - if (!pdata->poll_mode) > - dev_info(&pdev->dev, "Operating in interrupt mode" > - " using IRQ %d\n", davinci_spi->irq); > + dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); > > return ret; > > @@ -1220,7 +1055,7 @@ err: > * It will also call spi_bitbang_stop to destroy the work queue which was > * created by spi_bitbang_start. > */ > -static int __exit davinci_spi_remove(struct platform_device *pdev) > +static int __devexit davinci_spi_remove(struct platform_device *pdev) > { > struct davinci_spi *davinci_spi; > struct spi_master *master; > @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) > } > > static struct platform_driver davinci_spi_driver = { > - .driver.name = "spi_davinci", > - .remove = __exit_p(davinci_spi_remove), > + .driver = { > + .name = "spi_davinci", > + .owner = THIS_MODULE, > + }, > + .remove = __devexit_p(davinci_spi_remove), > }; Another candidate. Corrections to platform_driver structure and __devexit annotations. > > static int __init davinci_spi_init(void) > -- > 1.6.3.3 > > -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <AANLkTimu+G-5wTrdQ6YiWi60i+5uN9sydfsZKMKQX7_f-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <AANLkTimu+G-5wTrdQ6YiWi60i+5uN9sydfsZKMKQX7_f-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2010-08-02 14:10 ` Brian Niebuhr [not found] ` <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Brian Niebuhr @ 2010-08-02 14:10 UTC (permalink / raw) To: Grant Likely Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ Grant - That's fine - I understand your position. I do wish you had decided earlier that you weren't going to accept the patch in that form though so I could have decided whether I wanted to spend any more time on it. For my part, I've already sunk way more time into this than I ever intended, and I really have no clue how to break this patch down into smaller patches. I don't really care much if the patch gets accepted or not - I am just trying to help out all of the other users that are stuck with a broken driver like I was. Maybe if TI wants to give their customers a driver that actually works they'll pick it up and do the rest of the work that's necessary to get it accepted. I'm just way too swamped with other work to keep going on this. Thanks for your help though. Sorry to waste all of the time you've put into this. Brian On Sun, Aug 1, 2010 at 12:12 AM, Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> wrote: > On Wed, Jul 28, 2010 at 4:18 PM, Brian Niebuhr <bniebuhr3-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: >> INTRODUCTION >> >> I have been working on a custom OMAP-L138 board that has multiple spi >> devices (seven) on one controller. These devices have a wide range of >> transfer parameters (speed, phase, polarity, internal and gpio chip >> selects). During my testing I found multiple errors in the davinci spi >> driver as a result of this complex setup. The primary issues were: >> >> 1. There is a race condition due to the SPIBUF read busy-waits for slow >> devices >> 2. I found some DMA transfer length errors under some conditions >> 3. The chip select code caused extra byte transfers (with no chip >> select active) due to writes to SPIDAT1 >> 4. Several issues prevented using multiple SPI devices, especially >> the DMA code, as disucussed previously on the davinci list. >> >> The fixes to these problems were not simple. I ended up making fairly >> large changes to the driver, and those changes are contained in these >> patches. The full list of changes follows. >> >> CHANGE LIST >> >> 1. davinci_spi_chipelect() now performs both activation and deactivation >> of chip selects. This lets spi_bitbang fully control chip >> select activation, as intended by the SPI API. >> 2. Chip select activation does not cause extra writes to the SPI bus >> 3. Chip select activation does not use SPIDEF for control. This change >> will also allow for implementation of inverted (active high) >> chip selects in the future. >> 4. Added back gpio chip select capability from the old driver >> 5. Fixed prescale calculation for non-integer fractions of spi clock >> 6. Allow specification of SPI transfer parameters on a per-device >> (instead of per-controller) basis >> 7. Allow specification of polled, interrupt-based, or DMA operation on >> a per-device basis >> 8. Allow DMA with when more than one device is connected >> 9. Combined pio and dma txrx_bufs functions into one since they share >> large parts of their functionality, and to simplify item (8). >> 10. Use only SPIFMT0 to allow more than 4 devices >> >> TESTING >> >> I have tested the driver using a custom SPI stress test on my >> OMAP-L138-based board with three devices connected. I have tested >> configurations with all three devices polled, all three interrupt-based, >> all three DMA, and a mixture. >> >> I have compiled with the davinci_all_defconfig, but I don't have EVMs >> for the other davinci platforms to test with. >> >> Signed-off-by: Brian Niebuhr <bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org> > > Hi Brian, > > I'm getting a little frustrated, and I wouldn't be surprised if you're > getting a little frustrated too, but I cannot merge this as is. It is > just too big to be able to review sanely, when I know there are > bite-size chunks that can be factored out into separate patches and > can be merged independently. > > At a *bare minimum* I would need acks from several davinci users that > it is tested and working before I'd merge something like this, but > even then I'm not sure I would. It certainly will not make me happy. > It also means that when someone does have problems with the new driver > over the old that they won't have a hope of bisecting it to figure out > which change broken their system. There will be less pain all around > if you split it up instead. > > ... > > In fact, after taking another look at it, I insist. I can tell that > while major changes have been made, it is *still* the same driver with > changes that can be logically identified. Split it up. > > I'm more than happy to help you with the tools and techniques for > splitting a single monolithic patch into logical changes if you've not > done that before. Send me a private email if you prefer. > > Comments below: > >> --- >> arch/arm/mach-davinci/board-dm355-evm.c | 10 + >> arch/arm/mach-davinci/board-dm355-leopard.c | 10 + >> arch/arm/mach-davinci/board-dm365-evm.c | 10 + >> arch/arm/mach-davinci/dm355.c | 8 +- >> arch/arm/mach-davinci/dm365.c | 6 - >> arch/arm/mach-davinci/include/mach/spi.h | 35 +- >> drivers/spi/davinci_spi.c | 1098 ++++++++++++--------------- >> 7 files changed, 521 insertions(+), 656 deletions(-) >> >> diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c >> index a319101..ad8779b 100644 >> --- a/arch/arm/mach-davinci/board-dm355-evm.c >> +++ b/arch/arm/mach-davinci/board-dm355-evm.c >> @@ -32,6 +32,7 @@ >> #include <mach/nand.h> >> #include <mach/mmc.h> >> #include <mach/usb.h> >> +#include <mach/spi.h> >> >> /* NOTE: this is geared for the standard config, with a socketed >> * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you >> @@ -300,10 +301,19 @@ static struct spi_eeprom at25640a = { >> .flags = EE_ADDR2, >> }; >> >> +static struct davinci_spi_config at25640a_spi_cfg = { >> + .parity_enable = false, >> + .intr_level = 0, >> + .io_type = SPI_IO_TYPE_DMA, >> + .wdelay = 0, >> + .timer_disable = true, >> +}; >> + >> static struct spi_board_info dm355_evm_spi_info[] __initconst = { >> { >> .modalias = "at25", >> .platform_data = &at25640a, >> + .controller_data = &at25640a_spi_cfg, >> .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ >> .bus_num = 0, >> .chip_select = 0, >> diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c >> index f1d8132..b2d8d48 100644 >> --- a/arch/arm/mach-davinci/board-dm355-leopard.c >> +++ b/arch/arm/mach-davinci/board-dm355-leopard.c >> @@ -29,6 +29,7 @@ >> #include <mach/nand.h> >> #include <mach/mmc.h> >> #include <mach/usb.h> >> +#include <mach/spi.h> >> >> /* NOTE: this is geared for the standard config, with a socketed >> * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you >> @@ -222,10 +223,19 @@ static struct spi_eeprom at25640a = { >> .flags = EE_ADDR2, >> }; >> >> +static struct davinci_spi_config at25640a_spi_cfg = { >> + .parity_enable = false, >> + .intr_level = 0, >> + .io_type = SPI_IO_TYPE_DMA, >> + .wdelay = 0, >> + .timer_disable = true, >> +}; >> + >> static struct spi_board_info dm355_leopard_spi_info[] __initconst = { >> { >> .modalias = "at25", >> .platform_data = &at25640a, >> + .controller_data = &at25640a_spi_cfg, >> .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ >> .bus_num = 0, >> .chip_select = 0, >> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c >> index 5bb86b2..db85372 100644 >> --- a/arch/arm/mach-davinci/board-dm365-evm.c >> +++ b/arch/arm/mach-davinci/board-dm365-evm.c >> @@ -39,6 +39,7 @@ >> #include <mach/mmc.h> >> #include <mach/nand.h> >> #include <mach/keyscan.h> >> +#include <mach/spi.h> >> >> #include <media/tvp514x.h> >> >> @@ -579,10 +580,19 @@ static struct spi_eeprom at25640 = { >> .flags = EE_ADDR2, >> }; >> >> +static struct davinci_spi_config at25640_spi_cfg = { >> + .parity_enable = false, >> + .intr_level = 0, >> + .io_type = SPI_IO_TYPE_DMA, >> + .wdelay = 0, >> + .timer_disable = true, >> +}; >> + >> static struct spi_board_info dm365_evm_spi_info[] __initconst = { >> { >> .modalias = "at25", >> .platform_data = &at25640, >> + .controller_data = &at25640_spi_cfg, >> .max_speed_hz = 10 * 1000 * 1000, >> .bus_num = 0, >> .chip_select = 0, >> diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c >> index 3834781..b79b798 100644 >> --- a/arch/arm/mach-davinci/dm355.c >> +++ b/arch/arm/mach-davinci/dm355.c >> @@ -410,14 +410,8 @@ static struct resource dm355_spi0_resources[] = { >> }; >> >> static struct davinci_spi_platform_data dm355_spi0_pdata = { >> - .version = SPI_VERSION_1, >> + .version = SPI_VERSION_0, >> .num_chipselect = 2, >> - .clk_internal = 1, >> - .cs_hold = 1, >> - .intr_level = 0, >> - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ >> - .c2tdelay = 0, >> - .t2cdelay = 0, >> }; >> static struct platform_device dm355_spi0_device = { >> .name = "spi_davinci", >> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c >> index 652f4b6..4aea346 100644 >> --- a/arch/arm/mach-davinci/dm365.c >> +++ b/arch/arm/mach-davinci/dm365.c >> @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); >> static struct davinci_spi_platform_data dm365_spi0_pdata = { >> .version = SPI_VERSION_1, >> .num_chipselect = 2, >> - .clk_internal = 1, >> - .cs_hold = 1, >> - .intr_level = 0, >> - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ >> - .c2tdelay = 0, >> - .t2cdelay = 0, >> }; >> >> static struct resource dm365_spi0_resources[] = { >> diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h >> index 910efbf..3f77dab 100644 >> --- a/arch/arm/mach-davinci/include/mach/spi.h >> +++ b/arch/arm/mach-davinci/include/mach/spi.h >> @@ -19,26 +19,35 @@ >> #ifndef __ARCH_ARM_DAVINCI_SPI_H >> #define __ARCH_ARM_DAVINCI_SPI_H >> >> +#define SPI_INTERN_CS 0xFF >> + >> enum { >> - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ >> + SPI_VERSION_0, /* For DM355 (reduced features, no Tx interrupt) */ >> + SPI_VERSION_1, /* For DM365/DM6467 (reduced features) */ >> SPI_VERSION_2, /* For DA8xx */ >> }; >> >> struct davinci_spi_platform_data { >> u8 version; >> - u8 num_chipselect; >> - u8 wdelay; >> - u8 odd_parity; >> - u8 parity_enable; >> - u8 wait_enable; >> - u8 timer_disable; >> - u8 clk_internal; >> - u8 cs_hold; >> + u16 num_chipselect; >> + u8 *chip_sel; >> +}; >> + >> +struct davinci_spi_config { >> + bool odd_parity; >> + bool parity_enable; >> u8 intr_level; >> - u8 poll_mode; >> - u8 use_dma; >> - u8 c2tdelay; >> - u8 t2cdelay; >> + u8 io_type; >> +#define SPI_IO_TYPE_INTR 0 >> +#define SPI_IO_TYPE_POLL 1 >> +#define SPI_IO_TYPE_DMA 2 >> + u8 bytes_per_word; >> + u8 wdelay; >> + bool timer_disable; >> + u8 c2t_delay; >> + u8 t2c_delay; >> + u8 t2e_delay; >> + u8 c2e_delay; >> }; >> >> #endif /* __ARCH_ARM_DAVINCI_SPI_H */ >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c >> index b85090c..5c9e9ce 100644 >> --- a/drivers/spi/davinci_spi.c >> +++ b/drivers/spi/davinci_spi.c >> @@ -1,5 +1,6 @@ >> /* >> * Copyright (C) 2009 Texas Instruments. >> + * Copyright (C) 2010 EF Johnson Technologies >> * >> * This program is free software; you can redistribute it and/or modify >> * it under the terms of the GNU General Public License as published by >> @@ -27,21 +28,19 @@ >> #include <linux/dma-mapping.h> >> #include <linux/spi/spi.h> >> #include <linux/spi/spi_bitbang.h> >> -#include <linux/slab.h> >> >> #include <mach/spi.h> >> #include <mach/edma.h> >> >> #define SPI_NO_RESOURCE ((resource_size_t)-1) >> >> -#define SPI_MAX_CHIPSELECT 2 >> - >> #define CS_DEFAULT 0xFF >> >> #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1) >> -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 >> -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 >> -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 >> + >> +#define RX_DMA_INDEX 0 >> +#define TX_DMA_INDEX 1 >> +#define EVENTQ_DMA_INDEX 2 >> >> #define SPIFMT_PHASE_MASK BIT(16) >> #define SPIFMT_POLARITY_MASK BIT(17) >> @@ -53,9 +52,11 @@ >> #define SPIFMT_WDELAY_MASK 0x3f000000u >> #define SPIFMT_WDELAY_SHIFT 24 >> #define SPIFMT_CHARLEN_MASK 0x0000001Fu >> +#define SPIFMT_PRESCALE_SHIFT 8 >> >> /* SPIGCR1 */ >> -#define SPIGCR1_SPIENA_MASK 0x01000000u >> +#define SPIGCR1_SPIENA_MASK BIT(24) >> +#define SPIGCR1_POWERDOWN_MASK BIT(8) >> >> /* SPIPC0 */ >> #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ >> @@ -66,20 +67,38 @@ >> #define SPIPC0_EN0FUN_MASK BIT(0) >> >> #define SPIINT_MASKALL 0x0101035F >> +#define SPIINT_MASKINT 0x0000035F >> #define SPI_INTLVL_1 0x000001FFu >> #define SPI_INTLVL_0 0x00000000u >> >> /* SPIDAT1 */ >> +#define SPIDAT1_CSHOLD_MASK BIT(28) >> #define SPIDAT1_CSHOLD_SHIFT 28 >> +#define SPIDAT1_WDEL_MASK BIT(26) >> +#define SPIDAT1_CSNR_MASK 0x00FF0000u >> #define SPIDAT1_CSNR_SHIFT 16 >> +#define SPIDAT1_DFSEL_MASK (BIT(24 | BIT(25)) >> #define SPIGCR1_CLKMOD_MASK BIT(1) >> -#define SPIGCR1_MASTER_MASK BIT(0) >> +#define SPIGCR1_MASTER_MASK BIT(0) >> #define SPIGCR1_LOOPBACK_MASK BIT(16) >> >> /* SPIBUF */ >> #define SPIBUF_TXFULL_MASK BIT(29) >> #define SPIBUF_RXEMPTY_MASK BIT(31) >> >> +/* SPIDELAY */ >> +#define SPIDELAY_C2TDELAY_MASK 0xFF000000u >> +#define SPIDELAY_C2TDELAY_SHIFT 24 >> +#define SPIDELAY_T2CDELAY_MASK 0x00FF0000u >> +#define SPIDELAY_T2CDELAY_SHIFT 16 >> +#define SPIDELAY_T2EDELAY_MASK 0x0000FF00u >> +#define SPIDELAY_T2EDELAY_SHIFT 8 >> +#define SPIDELAY_C2EDELAY_MASK 0x000000FFu >> +#define SPIDELAY_C2EDELAY_SHIFT 0 >> + >> +/* SPIDEF */ >> +#define SPIDEF_CSDEF_MASK 0x000000FFu >> + >> /* Error Masks */ >> #define SPIFLG_DLEN_ERR_MASK BIT(0) >> #define SPIFLG_TIMEOUT_MASK BIT(1) >> @@ -90,11 +109,12 @@ >> #define SPIFLG_RX_INTR_MASK BIT(8) >> #define SPIFLG_TX_INTR_MASK BIT(9) >> #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) >> -#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \ >> +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ >> | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ >> | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ >> - | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \ >> - | SPIFLG_TX_INTR_MASK \ >> + | SPIFLG_OVRRUN_MASK) >> +#define SPIFLG_MASK (SPIFLG_ERROR_MASK \ >> + | SPIFLG_RX_INTR_MASK | SPIFLG_TX_INTR_MASK \ >> | SPIFLG_BUF_INIT_ACTIVE_MASK) >> >> #define SPIINT_DLEN_ERR_INTR BIT(0) >> @@ -139,11 +159,10 @@ >> #define TGINTVEC0 0x60 >> #define TGINTVEC1 0x64 >> >> -struct davinci_spi_slave { >> - u32 cmd_to_write; >> - u32 clk_ctrl_to_write; >> - u32 bytes_per_word; >> - u8 active_cs; >> +const char * const io_type_names[] = { >> + [SPI_IO_TYPE_INTR] = "Interrupt", >> + [SPI_IO_TYPE_POLL] = "Polled", >> + [SPI_IO_TYPE_DMA] = "DMA", >> }; >> >> /* We have 2 DMA channels per CS, one for RX and one for TX */ >> @@ -152,10 +171,8 @@ struct davinci_spi_dma { >> int dma_rx_channel; >> int dma_tx_sync_dev; >> int dma_rx_sync_dev; >> + int dummy_param_slot; >> enum dma_event_q eventq; >> - >> - struct completion dma_tx_completion; >> - struct completion dma_rx_completion; >> }; >> >> /* SPI Controller driver's private data. */ >> @@ -173,51 +190,53 @@ struct davinci_spi { >> const void *tx; >> void *rx; >> u8 *tmp_buf; >> - int count; >> - struct davinci_spi_dma *dma_channels; >> - struct davinci_spi_platform_data *pdata; >> + int rcount; >> + int wcount; >> + u32 errors; >> + struct davinci_spi_dma dma_channels; >> + struct davinci_spi_platform_data *pdata; >> >> void (*get_rx)(u32 rx_data, struct davinci_spi *); >> u32 (*get_tx)(struct davinci_spi *); >> - >> - struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT]; >> }; >> >> -static unsigned use_dma; >> - >> static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) >> { >> - u8 *rx = davinci_spi->rx; >> - >> - *rx++ = (u8)data; >> - davinci_spi->rx = rx; >> + if (davinci_spi->rx) { >> + u8 *rx = davinci_spi->rx; >> + *rx++ = (u8)data; >> + davinci_spi->rx = rx; >> + } >> } >> >> static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) >> { >> - u16 *rx = davinci_spi->rx; >> - >> - *rx++ = (u16)data; >> - davinci_spi->rx = rx; >> + if (davinci_spi->rx) { >> + u16 *rx = davinci_spi->rx; >> + *rx++ = (u16)data; >> + davinci_spi->rx = rx; >> + } >> } >> >> static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) >> { >> - u32 data; >> - const u8 *tx = davinci_spi->tx; >> - >> - data = *tx++; >> - davinci_spi->tx = tx; >> + u32 data = 0; >> + if (davinci_spi->tx) { >> + const u8 *tx = davinci_spi->tx; >> + data = *tx++; >> + davinci_spi->tx = tx; >> + } >> return data; >> } > > Here's an excellent candidate for a separate patch. Validation of the > rx/tx buffer before transfering data to/from it. > >> >> static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) >> { >> - u32 data; >> - const u16 *tx = davinci_spi->tx; >> - >> - data = *tx++; >> - davinci_spi->tx = tx; >> + u32 data = 0; >> + if (davinci_spi->tx) { >> + const u16 *tx = davinci_spi->tx; >> + data = *tx++; >> + davinci_spi->tx = tx; >> + } >> return data; >> } >> >> @@ -237,26 +256,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) >> iowrite32(v, addr); >> } >> >> -static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num) >> -{ >> - set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); >> -} >> - >> -static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num) >> -{ >> - clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits); >> -} >> - >> -static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) >> -{ >> - struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); >> - >> - if (enable) >> - set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); >> - else >> - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); >> -} >> - >> /* >> * Interface to control the chip select signal >> */ >> @@ -264,25 +263,54 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) >> { >> struct davinci_spi *davinci_spi; >> struct davinci_spi_platform_data *pdata; >> - u32 data1_reg_val = 0; >> + u8 i, chip_sel = spi->chip_select; >> + u32 spidat1; >> + u16 spidat1_cfg; >> >> davinci_spi = spi_master_get_devdata(spi->master); >> pdata = davinci_spi->pdata; >> >> - /* >> - * Board specific chip select logic decides the polarity and cs >> - * line for the controller >> - */ >> - if (value == BITBANG_CS_INACTIVE) { >> - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); >> - >> - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; >> - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); >> + spidat1 = SPIDAT1_CSNR_MASK; >> + if (value == BITBANG_CS_ACTIVE) >> + spidat1 |= SPIDAT1_CSHOLD_MASK; >> + else >> + spidat1 |= SPIDAT1_WDEL_MASK; >> >> - while ((ioread32(davinci_spi->base + SPIBUF) >> - & SPIBUF_RXEMPTY_MASK) == 0) >> - cpu_relax(); >> + if (pdata->chip_sel == NULL) { >> + if (value == BITBANG_CS_ACTIVE) >> + spidat1 &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT); >> + } else { >> + for (i = 0; i < pdata->num_chipselect; i++) { >> + if (pdata->chip_sel[i] == SPI_INTERN_CS) { >> + if ((i == chip_sel) && >> + (value == BITBANG_CS_ACTIVE)) { >> + spidat1 &= ~((0x1 << chip_sel) >> + << SPIDAT1_CSNR_SHIFT); >> + } >> + } else { >> + if (value == BITBANG_CS_INACTIVE) >> + gpio_set_value(pdata->chip_sel[i], 1); >> + else if (i == chip_sel) >> + gpio_set_value(pdata->chip_sel[i], 0); >> + } >> + } >> } >> + >> + spidat1_cfg = spidat1 >> SPIDAT1_CSNR_SHIFT; >> + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); >> +} >> + >> +/** >> + * davinci_spi_get_prescale - Calculates the correct prescale value >> + * @max_speed_hz: the maximum rate the SPI clock can run at >> + * >> + * This function calculates the prescale value that generates a clock rate >> + * less than or equal to the specified maximum >> + */ >> +static inline u32 davinci_spi_get_prescale(struct davinci_spi *davinci_spi, >> + u32 max_speed_hz) >> +{ >> + return ((clk_get_rate(davinci_spi->clk) - 1) / max_speed_hz) & 0xff; >> } >> >> /** >> @@ -297,14 +325,15 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) >> static int davinci_spi_setup_transfer(struct spi_device *spi, >> struct spi_transfer *t) >> { >> - >> struct davinci_spi *davinci_spi; >> struct davinci_spi_platform_data *pdata; >> + struct davinci_spi_config *spi_cfg; >> u8 bits_per_word = 0; >> - u32 hz = 0, prescale = 0, clkspeed; >> + u32 hz = 0, spifmt = 0, prescale, delay = 0; >> >> davinci_spi = spi_master_get_devdata(spi->master); >> pdata = davinci_spi->pdata; >> + spi_cfg = spi->controller_data; >> >> if (t) { >> bits_per_word = t->bits_per_word; >> @@ -322,76 +351,112 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, >> if (bits_per_word <= 8 && bits_per_word >= 2) { >> davinci_spi->get_rx = davinci_spi_rx_buf_u8; >> davinci_spi->get_tx = davinci_spi_tx_buf_u8; >> - davinci_spi->slave[spi->chip_select].bytes_per_word = 1; >> + spi_cfg->bytes_per_word = 1; >> } else if (bits_per_word <= 16 && bits_per_word >= 2) { >> davinci_spi->get_rx = davinci_spi_rx_buf_u16; >> davinci_spi->get_tx = davinci_spi_tx_buf_u16; >> - davinci_spi->slave[spi->chip_select].bytes_per_word = 2; >> + spi_cfg->bytes_per_word = 2; >> } else >> return -EINVAL; >> >> if (!hz) >> hz = spi->max_speed_hz; >> >> - clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK, >> - spi->chip_select); >> - set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, >> - spi->chip_select); >> + prescale = davinci_spi_get_prescale(davinci_spi, hz); >> + spifmt |= (prescale << SPIFMT_PRESCALE_SHIFT); >> + >> + spifmt |= (bits_per_word & 0x1f); >> + >> + if (spi->mode & SPI_LSB_FIRST) >> + spifmt |= SPIFMT_SHIFTDIR_MASK; >> + >> + if (spi->mode & SPI_CPOL) >> + spifmt |= SPIFMT_POLARITY_MASK; >> + >> + if (!(spi->mode & SPI_CPHA)) >> + spifmt |= SPIFMT_PHASE_MASK; >> + >> + if (davinci_spi->version == SPI_VERSION_2) { >> + spifmt |= ((spi_cfg->wdelay << SPIFMT_WDELAY_SHIFT) >> + & SPIFMT_WDELAY_MASK); >> + >> + if (spi_cfg->odd_parity) >> + spifmt |= SPIFMT_ODD_PARITY_MASK; >> + >> + if (spi_cfg->parity_enable) >> + spifmt |= SPIFMT_PARITYENA_MASK; >> + >> + if (spi->mode & SPI_READY) { >> + spifmt |= SPIFMT_WAITENA_MASK; >> + delay |= (spi_cfg->t2e_delay >> + << SPIDELAY_T2EDELAY_SHIFT) >> + & SPIDELAY_T2EDELAY_MASK; >> + delay |= (spi_cfg->c2e_delay >> + << SPIDELAY_C2EDELAY_SHIFT) >> + & SPIDELAY_C2EDELAY_MASK; >> + } >> + >> + if (spi_cfg->timer_disable) { >> + spifmt |= SPIFMT_DISTIMER_MASK; >> + } else { >> + delay |= (spi_cfg->c2t_delay >> + << SPIDELAY_C2TDELAY_SHIFT) >> + & SPIDELAY_C2TDELAY_MASK; >> + delay |= (spi_cfg->t2c_delay >> + << SPIDELAY_T2CDELAY_SHIFT) >> + & SPIDELAY_T2CDELAY_MASK; >> + } >> >> - clkspeed = clk_get_rate(davinci_spi->clk); >> - if (hz > clkspeed / 2) >> - prescale = 1 << 8; >> - if (hz < clkspeed / 256) >> - prescale = 255 << 8; >> - if (!prescale) >> - prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00; >> + iowrite32(delay, davinci_spi->base + SPIDELAY); >> + } >> + >> + iowrite32(spifmt, davinci_spi->base + SPIFMT0); >> >> - clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); >> - set_fmt_bits(davinci_spi->base, prescale, spi->chip_select); >> + if (spi_cfg->intr_level) >> + iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); >> + else >> + iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); >> + >> + if (spi->mode & SPI_LOOP) >> + set_io_bits(davinci_spi->base + SPIGCR1, >> + SPIGCR1_LOOPBACK_MASK); >> + else >> + clear_io_bits(davinci_spi->base + SPIGCR1, >> + SPIGCR1_LOOPBACK_MASK); >> >> return 0; >> } >> >> static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) >> { >> - struct spi_device *spi = (struct spi_device *)data; >> - struct davinci_spi *davinci_spi; >> + struct davinci_spi *davinci_spi = data; >> struct davinci_spi_dma *davinci_spi_dma; >> struct davinci_spi_platform_data *pdata; >> >> - davinci_spi = spi_master_get_devdata(spi->master); >> - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); >> + davinci_spi_dma = &(davinci_spi->dma_channels); >> pdata = davinci_spi->pdata; >> >> + edma_stop(davinci_spi_dma->dma_rx_channel); >> + >> if (ch_status == DMA_COMPLETE) >> - edma_stop(davinci_spi_dma->dma_rx_channel); >> - else >> - edma_clean_channel(davinci_spi_dma->dma_rx_channel); >> + davinci_spi->rcount = 0; >> >> - complete(&davinci_spi_dma->dma_rx_completion); >> - /* We must disable the DMA RX request */ >> - davinci_spi_set_dma_req(spi, 0); >> + complete(&davinci_spi->done); >> } >> >> static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) >> { >> - struct spi_device *spi = (struct spi_device *)data; >> - struct davinci_spi *davinci_spi; >> + struct davinci_spi *davinci_spi = data; >> struct davinci_spi_dma *davinci_spi_dma; >> struct davinci_spi_platform_data *pdata; >> >> - davinci_spi = spi_master_get_devdata(spi->master); >> - davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]); >> + davinci_spi_dma = &(davinci_spi->dma_channels); >> pdata = davinci_spi->pdata; >> >> - if (ch_status == DMA_COMPLETE) >> - edma_stop(davinci_spi_dma->dma_tx_channel); >> - else >> - edma_clean_channel(davinci_spi_dma->dma_tx_channel); >> + edma_stop(davinci_spi_dma->dma_tx_channel); >> >> - complete(&davinci_spi_dma->dma_tx_completion); >> - /* We must disable the DMA TX request */ >> - davinci_spi_set_dma_req(spi, 0); >> + if (ch_status == DMA_COMPLETE) >> + davinci_spi->wcount = 0; >> } >> >> static int davinci_spi_request_dma(struct spi_device *spi) >> @@ -403,30 +468,51 @@ static int davinci_spi_request_dma(struct spi_device *spi) >> int r; >> >> davinci_spi = spi_master_get_devdata(spi->master); >> - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; >> + davinci_spi_dma = &davinci_spi->dma_channels; >> pdata = davinci_spi->pdata; >> sdev = davinci_spi->bitbang.master->dev.parent; >> >> r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, >> - davinci_spi_dma_rx_callback, spi, >> + davinci_spi_dma_rx_callback, davinci_spi, >> davinci_spi_dma->eventq); >> if (r < 0) { >> - dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); >> - return -EAGAIN; >> + dev_dbg(sdev, "Unable to request DMA channel for MibSPI RX\n"); >> + r = -EAGAIN; >> + goto rx_dma_failed; >> } >> davinci_spi_dma->dma_rx_channel = r; >> + >> r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, >> - davinci_spi_dma_tx_callback, spi, >> + davinci_spi_dma_tx_callback, davinci_spi, >> davinci_spi_dma->eventq); >> if (r < 0) { >> - edma_free_channel(davinci_spi_dma->dma_rx_channel); >> - davinci_spi_dma->dma_rx_channel = -1; >> - dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); >> - return -EAGAIN; >> + dev_dbg(sdev, "Unable to request DMA channel for MibSPI TX\n"); >> + r = -EAGAIN; >> + goto tx_dma_failed; >> } >> davinci_spi_dma->dma_tx_channel = r; >> >> + r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_sync_dev), >> + EDMA_SLOT_ANY); >> + if (r < 0) { >> + dev_dbg(sdev, "Unable to request SPI DMA param slot\n"); >> + r = -EAGAIN; >> + goto param_failed; >> + } >> + davinci_spi_dma->dummy_param_slot = r; >> + edma_link(davinci_spi_dma->dummy_param_slot, >> + davinci_spi_dma->dummy_param_slot); >> + >> return 0; >> + >> +param_failed: >> + edma_free_channel(davinci_spi_dma->dma_tx_channel); >> + davinci_spi_dma->dma_tx_channel = -1; >> +tx_dma_failed: >> + edma_free_channel(davinci_spi_dma->dma_rx_channel); >> + davinci_spi_dma->dma_rx_channel = -1; >> +rx_dma_failed: >> + return r; >> } >> >> /** >> @@ -438,129 +524,54 @@ static int davinci_spi_request_dma(struct spi_device *spi) >> >> static int davinci_spi_setup(struct spi_device *spi) >> { >> - int retval; >> + int retval = 0; >> struct davinci_spi *davinci_spi; >> - struct davinci_spi_dma *davinci_spi_dma; >> - struct device *sdev; >> + struct davinci_spi_dma *davinci_dma; >> + struct davinci_spi_platform_data *pdata; >> + struct davinci_spi_config *spi_cfg; >> + u32 prescale; >> >> davinci_spi = spi_master_get_devdata(spi->master); >> - sdev = davinci_spi->bitbang.master->dev.parent; >> + pdata = davinci_spi->pdata; >> + spi_cfg = (struct davinci_spi_config *)spi->controller_data; >> + davinci_dma = &(davinci_spi->dma_channels); >> >> /* if bits per word length is zero then set it default 8 */ >> if (!spi->bits_per_word) >> spi->bits_per_word = 8; >> >> - davinci_spi->slave[spi->chip_select].cmd_to_write = 0; >> + if (!(spi->mode & SPI_NO_CS)) { >> + if ((pdata->chip_sel == NULL) || >> + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) >> + set_io_bits(davinci_spi->base + SPIPC0, >> + 1 << spi->chip_select); >> >> - if (use_dma && davinci_spi->dma_channels) { >> - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; >> - >> - if ((davinci_spi_dma->dma_rx_channel == -1) >> - || (davinci_spi_dma->dma_tx_channel == -1)) { >> - retval = davinci_spi_request_dma(spi); >> - if (retval < 0) >> - return retval; >> - } >> - } >> - >> - /* >> - * SPI in DaVinci and DA8xx operate between >> - * 600 KHz and 50 MHz >> - */ >> - if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) { >> - dev_dbg(sdev, "Operating frequency is not in acceptable " >> - "range\n"); >> - return -EINVAL; >> } >> >> - /* >> - * Set up SPIFMTn register, unique to this chipselect. >> - * >> - * NOTE: we could do all of these with one write. Also, some >> - * of the "version 2" features are found in chips that don't >> - * support all of them... >> - */ >> - if (spi->mode & SPI_LSB_FIRST) >> - set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK, >> - spi->chip_select); >> + if (spi->mode & SPI_READY) >> + set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); >> >> - if (spi->mode & SPI_CPOL) >> - set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK, >> - spi->chip_select); >> + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { >> + davinci_dma = &(davinci_spi->dma_channels); >> >> - if (!(spi->mode & SPI_CPHA)) >> - set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK, >> - spi->chip_select); >> + if ((davinci_dma->dma_tx_sync_dev == SPI_NO_RESOURCE) || >> + (davinci_dma->dma_rx_sync_dev == SPI_NO_RESOURCE) || >> + (davinci_dma->eventq == SPI_NO_RESOURCE)) >> + spi_cfg->io_type = SPI_IO_TYPE_INTR; >> + else if ((davinci_dma->dma_rx_channel == -1) || >> + (davinci_dma->dma_tx_channel == -1)) >> + retval = davinci_spi_request_dma(spi); >> + } >> >> /* >> - * Version 1 hardware supports two basic SPI modes: >> - * - Standard SPI mode uses 4 pins, with chipselect >> - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) >> - * (distinct from SPI_3WIRE, with just one data wire; >> - * or similar variants without MOSI or without MISO) >> - * >> - * Version 2 hardware supports an optional handshaking signal, >> - * so it can support two more modes: >> - * - 5 pin SPI variant is standard SPI plus SPI_READY >> - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) >> + * Validate desired clock rate >> */ >> + prescale = davinci_spi_get_prescale(davinci_spi, spi->max_speed_hz); >> + if ((prescale < 2) || (prescale > 255)) >> + return -EINVAL; >> >> - if (davinci_spi->version == SPI_VERSION_2) { >> - clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK, >> - spi->chip_select); >> - set_fmt_bits(davinci_spi->base, >> - (davinci_spi->pdata->wdelay >> - << SPIFMT_WDELAY_SHIFT) >> - & SPIFMT_WDELAY_MASK, >> - spi->chip_select); >> - >> - if (davinci_spi->pdata->odd_parity) >> - set_fmt_bits(davinci_spi->base, >> - SPIFMT_ODD_PARITY_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, >> - SPIFMT_ODD_PARITY_MASK, >> - spi->chip_select); >> - >> - if (davinci_spi->pdata->parity_enable) >> - set_fmt_bits(davinci_spi->base, >> - SPIFMT_PARITYENA_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, >> - SPIFMT_PARITYENA_MASK, >> - spi->chip_select); >> - >> - if (davinci_spi->pdata->wait_enable) >> - set_fmt_bits(davinci_spi->base, >> - SPIFMT_WAITENA_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, >> - SPIFMT_WAITENA_MASK, >> - spi->chip_select); >> - >> - if (davinci_spi->pdata->timer_disable) >> - set_fmt_bits(davinci_spi->base, >> - SPIFMT_DISTIMER_MASK, >> - spi->chip_select); >> - else >> - clear_fmt_bits(davinci_spi->base, >> - SPIFMT_DISTIMER_MASK, >> - spi->chip_select); >> - } >> - >> - retval = davinci_spi_setup_transfer(spi, NULL); >> + dev_info(&spi->dev, "DaVinci SPI driver in %s mode\n", >> + io_type_names[spi_cfg->io_type]); >> >> return retval; >> } >> @@ -569,50 +580,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) >> { >> struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); >> struct davinci_spi_dma *davinci_spi_dma; >> + struct davinci_spi_platform_data *pdata; >> >> - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; >> - >> - if (use_dma && davinci_spi->dma_channels) { >> - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; >> - >> - if ((davinci_spi_dma->dma_rx_channel != -1) >> - && (davinci_spi_dma->dma_tx_channel != -1)) { >> - edma_free_channel(davinci_spi_dma->dma_tx_channel); >> - edma_free_channel(davinci_spi_dma->dma_rx_channel); >> - } >> - } >> -} >> - >> -static int davinci_spi_bufs_prep(struct spi_device *spi, >> - struct davinci_spi *davinci_spi) >> -{ >> - int op_mode = 0; >> - >> - /* >> - * REVISIT unless devices disagree about SPI_LOOP or >> - * SPI_READY (SPI_NO_CS only allows one device!), this >> - * should not need to be done before each message... >> - * optimize for both flags staying cleared. >> - */ >> - >> - op_mode = SPIPC0_DIFUN_MASK >> - | SPIPC0_DOFUN_MASK >> - | SPIPC0_CLKFUN_MASK; >> - if (!(spi->mode & SPI_NO_CS)) >> - op_mode |= 1 << spi->chip_select; >> - if (spi->mode & SPI_READY) >> - op_mode |= SPIPC0_SPIENA_MASK; >> + davinci_spi_dma = &davinci_spi->dma_channels; >> + pdata = davinci_spi->pdata; >> >> - iowrite32(op_mode, davinci_spi->base + SPIPC0); >> + if (davinci_spi_dma->dma_rx_channel != -1) >> + edma_free_channel(davinci_spi_dma->dma_rx_channel); >> >> - if (spi->mode & SPI_LOOP) >> - set_io_bits(davinci_spi->base + SPIGCR1, >> - SPIGCR1_LOOPBACK_MASK); >> - else >> - clear_io_bits(davinci_spi->base + SPIGCR1, >> - SPIGCR1_LOOPBACK_MASK); >> + if (davinci_spi_dma->dma_tx_channel != -1) >> + edma_free_channel(davinci_spi_dma->dma_tx_channel); >> >> - return 0; >> + if (davinci_spi_dma->dummy_param_slot != -1) >> + edma_free_slot(davinci_spi_dma->dummy_param_slot); >> } >> >> static int davinci_spi_check_error(struct davinci_spi *davinci_spi, >> @@ -660,355 +640,242 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi, >> } >> >> /** >> - * davinci_spi_bufs - functions which will handle transfer data >> - * @spi: spi device on which data transfer to be done >> - * @t: spi transfer in which transfer info is filled >> + * davinci_spi_process_events - check for and handle any SPI controller events >> + * @davinci_spi: the controller data >> * >> - * This function will put data to be transferred into data register >> - * of SPI controller and then wait until the completion will be marked >> - * by the IRQ Handler. >> + * This function will check the SPIFLG register and handle any events that are >> + * detected there >> */ >> -static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) >> +static int davinci_spi_process_events(struct davinci_spi *davinci_spi) >> { >> - struct davinci_spi *davinci_spi; >> - int int_status, count, ret; >> - u8 conv, tmp; >> - u32 tx_data, data1_reg_val; >> - u32 buf_val, flg_val; >> - struct davinci_spi_platform_data *pdata; >> - >> - davinci_spi = spi_master_get_devdata(spi->master); >> - pdata = davinci_spi->pdata; >> - >> - davinci_spi->tx = t->tx_buf; >> - davinci_spi->rx = t->rx_buf; >> - >> - /* convert len to words based on bits_per_word */ >> - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; >> - davinci_spi->count = t->len / conv; >> - >> - INIT_COMPLETION(davinci_spi->done); >> - >> - ret = davinci_spi_bufs_prep(spi, davinci_spi); >> - if (ret) >> - return ret; >> - >> - /* Enable SPI */ >> - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); >> - >> - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | >> - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), >> - davinci_spi->base + SPIDELAY); >> - >> - count = davinci_spi->count; >> - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; >> - tmp = ~(0x1 << spi->chip_select); >> - >> - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); >> - >> - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; >> - >> - while ((ioread32(davinci_spi->base + SPIBUF) >> - & SPIBUF_RXEMPTY_MASK) == 0) >> - cpu_relax(); >> - >> - /* Determine the command to execute READ or WRITE */ >> - if (t->tx_buf) { >> - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); >> - >> - while (1) { >> - tx_data = davinci_spi->get_tx(davinci_spi); >> - >> - data1_reg_val &= ~(0xFFFF); >> - data1_reg_val |= (0xFFFF & tx_data); >> - >> - buf_val = ioread32(davinci_spi->base + SPIBUF); >> - if ((buf_val & SPIBUF_TXFULL_MASK) == 0) { >> - iowrite32(data1_reg_val, >> - davinci_spi->base + SPIDAT1); >> - >> - count--; >> - } >> - while (ioread32(davinci_spi->base + SPIBUF) >> - & SPIBUF_RXEMPTY_MASK) >> - cpu_relax(); >> - >> - /* getting the returned byte */ >> - if (t->rx_buf) { >> - buf_val = ioread32(davinci_spi->base + SPIBUF); >> - davinci_spi->get_rx(buf_val, davinci_spi); >> - } >> - if (count <= 0) >> - break; >> - } >> - } else { >> - if (pdata->poll_mode) { >> - while (1) { >> - /* keeps the serial clock going */ >> - if ((ioread32(davinci_spi->base + SPIBUF) >> - & SPIBUF_TXFULL_MASK) == 0) >> - iowrite32(data1_reg_val, >> - davinci_spi->base + SPIDAT1); >> - >> - while (ioread32(davinci_spi->base + SPIBUF) & >> - SPIBUF_RXEMPTY_MASK) >> - cpu_relax(); >> - >> - flg_val = ioread32(davinci_spi->base + SPIFLG); >> - buf_val = ioread32(davinci_spi->base + SPIBUF); >> - >> - davinci_spi->get_rx(buf_val, davinci_spi); >> - >> - count--; >> - if (count <= 0) >> - break; >> - } >> - } else { /* Receive in Interrupt mode */ >> - int i; >> - >> - for (i = 0; i < davinci_spi->count; i++) { >> - set_io_bits(davinci_spi->base + SPIINT, >> - SPIINT_BITERR_INTR >> - | SPIINT_OVRRUN_INTR >> - | SPIINT_RX_INTR); >> - >> - iowrite32(data1_reg_val, >> - davinci_spi->base + SPIDAT1); >> - >> - while (ioread32(davinci_spi->base + SPIINT) & >> - SPIINT_RX_INTR) >> - cpu_relax(); >> - } >> - iowrite32((data1_reg_val & 0x0ffcffff), >> - davinci_spi->base + SPIDAT1); >> - } >> + u32 status, tx_data, rx_data, spidat1; >> + u8 tx_word = 0; >> + >> + status = ioread32(davinci_spi->base + SPIFLG); >> + >> + if ((davinci_spi->version != SPI_VERSION_0) && >> + (likely(status & SPIFLG_TX_INTR_MASK)) && >> + (likely(davinci_spi->wcount > 0))) >> + tx_word = 1; >> + >> + if (likely(status & SPIFLG_RX_INTR_MASK)) { >> + rx_data = ioread32(davinci_spi->base + SPIBUF) & 0xFFFF; >> + davinci_spi->get_rx(rx_data, davinci_spi); >> + davinci_spi->rcount--; >> + if ((davinci_spi->version == SPI_VERSION_0) && >> + (likely(davinci_spi->wcount > 0))) >> + tx_word = 1; >> } >> >> - /* >> - * Check for bit error, desync error,parity error,timeout error and >> - * receive overflow errors >> - */ >> - int_status = ioread32(davinci_spi->base + SPIFLG); >> - >> - ret = davinci_spi_check_error(davinci_spi, int_status); >> - if (ret != 0) >> - return ret; >> + if (unlikely(status & SPIFLG_ERROR_MASK)) { >> + davinci_spi->errors = (status & SPIFLG_ERROR_MASK); >> + return -1; >> + } >> >> - /* SPI Framework maintains the count only in bytes so convert back */ >> - davinci_spi->count *= conv; >> + if (likely(tx_word)) { >> + spidat1 = ioread32(davinci_spi->base + SPIDAT1); >> + davinci_spi->wcount--; >> + tx_data = davinci_spi->get_tx(davinci_spi); >> + spidat1 &= 0xFFFF0000; >> + spidat1 |= (tx_data & 0xFFFF); >> + iowrite32(spidat1, davinci_spi->base + SPIDAT1); >> + } >> >> - return t->len; >> + return 0; >> } >> >> -#define DAVINCI_DMA_DATA_TYPE_S8 0x01 >> -#define DAVINCI_DMA_DATA_TYPE_S16 0x02 >> -#define DAVINCI_DMA_DATA_TYPE_S32 0x04 >> - >> -static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) >> +/** >> + * davinci_spi_txrx_bufs - function which will handle transfer data >> + * @spi: spi device on which data transfer to be done >> + * @t: spi transfer in which transfer info is filled >> + * >> + * This function will put data to be transferred into data register >> + * of SPI controller and then wait until the completion will be marked >> + * by the IRQ Handler. >> + */ >> +static int davinci_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) >> { >> struct davinci_spi *davinci_spi; >> - int int_status = 0; >> - int count, temp_count; >> - u8 conv = 1; >> - u8 tmp; >> - u32 data1_reg_val; >> - struct davinci_spi_dma *davinci_spi_dma; >> - int word_len, data_type, ret; >> - unsigned long tx_reg, rx_reg; >> + int data_type, ret = 0; >> + u32 tx_data, spidat1; >> + u16 tx_buf_count = 0, rx_buf_count = 0; >> + struct davinci_spi_config *spi_cfg; >> struct davinci_spi_platform_data *pdata; >> + struct davinci_spi_dma *davinci_dma; >> struct device *sdev; >> + dma_addr_t tx_reg, rx_reg; >> + void *tx_buf, *rx_buf; >> + struct edmacc_param rx_param, tx_param; >> >> davinci_spi = spi_master_get_devdata(spi->master); >> pdata = davinci_spi->pdata; >> - sdev = davinci_spi->bitbang.master->dev.parent; >> - >> - davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; >> - >> - tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; >> - rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; >> + spi_cfg = (struct davinci_spi_config *)spi->controller_data; >> + davinci_dma = &(davinci_spi->dma_channels); >> >> davinci_spi->tx = t->tx_buf; >> davinci_spi->rx = t->rx_buf; >> + davinci_spi->wcount = t->len / spi_cfg->bytes_per_word; >> + davinci_spi->rcount = davinci_spi->wcount; >> + davinci_spi->errors = 0; >> >> - /* convert len to words based on bits_per_word */ >> - conv = davinci_spi->slave[spi->chip_select].bytes_per_word; >> - davinci_spi->count = t->len / conv; >> + spidat1 = ioread32(davinci_spi->base + SPIDAT1); >> >> - INIT_COMPLETION(davinci_spi->done); >> - >> - init_completion(&davinci_spi_dma->dma_rx_completion); >> - init_completion(&davinci_spi_dma->dma_tx_completion); >> - >> - word_len = conv * 8; >> - >> - if (word_len <= 8) >> - data_type = DAVINCI_DMA_DATA_TYPE_S8; >> - else if (word_len <= 16) >> - data_type = DAVINCI_DMA_DATA_TYPE_S16; >> - else if (word_len <= 32) >> - data_type = DAVINCI_DMA_DATA_TYPE_S32; >> - else >> - return -EINVAL; >> - >> - ret = davinci_spi_bufs_prep(spi, davinci_spi); >> - if (ret) >> - return ret; >> - >> - /* Put delay val if required */ >> - iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) | >> - (pdata->t2cdelay << SPI_T2CDELAY_SHIFT), >> - davinci_spi->base + SPIDELAY); >> - >> - count = davinci_spi->count; /* the number of elements */ >> - data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT; >> - >> - /* CS default = 0xFF */ >> - tmp = ~(0x1 << spi->chip_select); >> - >> - clear_io_bits(davinci_spi->base + SPIDEF, ~tmp); >> - >> - data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT; >> - >> - /* disable all interrupts for dma transfers */ >> - clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); >> - /* Disable SPI to write configuration bits in SPIDAT */ >> - clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); >> - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); >> - /* Enable SPI */ >> + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); >> set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); >> >> - while ((ioread32(davinci_spi->base + SPIBUF) >> - & SPIBUF_RXEMPTY_MASK) == 0) >> - cpu_relax(); >> - >> + INIT_COMPLETION(davinci_spi->done); >> >> - if (t->tx_buf) { >> - t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, >> - DMA_TO_DEVICE); >> - if (dma_mapping_error(&spi->dev, t->tx_dma)) { >> - dev_dbg(sdev, "Unable to DMA map a %d bytes" >> - " TX buffer\n", count); >> - return -ENOMEM; >> + if ((spi_cfg->io_type == SPI_IO_TYPE_INTR) || >> + (spi_cfg->io_type == SPI_IO_TYPE_POLL)) { >> + >> + if (spi_cfg->io_type == SPI_IO_TYPE_INTR) >> + set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); >> + >> + /* start the transfer */ >> + davinci_spi->wcount--; >> + tx_data = davinci_spi->get_tx(davinci_spi); >> + spidat1 &= 0xFFFF0000; >> + spidat1 |= (tx_data & 0xFFFF); >> + iowrite32(spidat1, davinci_spi->base + SPIDAT1); >> + >> + } else if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { >> + data_type = spi_cfg->bytes_per_word; >> + tx_reg = (dma_addr_t)davinci_spi->pbase + SPIDAT1; >> + rx_reg = (dma_addr_t)davinci_spi->pbase + SPIBUF; >> + >> + if (t->tx_buf) { >> + tx_buf = ((void *)t->tx_buf); >> + tx_buf_count = davinci_spi->wcount; >> + } else { >> + tx_buf = (void *)davinci_spi->tmp_buf; >> + tx_buf_count = SPI_BUFSIZ; >> } >> - temp_count = count; >> - } else { >> - /* We need TX clocking for RX transaction */ >> - t->tx_dma = dma_map_single(&spi->dev, >> - (void *)davinci_spi->tmp_buf, count + 1, >> - DMA_TO_DEVICE); >> - if (dma_mapping_error(&spi->dev, t->tx_dma)) { >> - dev_dbg(sdev, "Unable to DMA map a %d bytes" >> - " TX tmp buffer\n", count); >> - return -ENOMEM; >> + if (t->rx_buf) { >> + rx_buf = (void *)t->rx_buf; >> + rx_buf_count = davinci_spi->rcount; >> + } else { >> + rx_buf = (void *)davinci_spi->tmp_buf; >> + rx_buf_count = SPI_BUFSIZ; >> } >> - temp_count = count + 1; >> + >> + t->tx_dma = dma_map_single(&spi->dev, tx_buf, >> + tx_buf_count, DMA_TO_DEVICE); >> + t->rx_dma = dma_map_single(&spi->dev, rx_buf, >> + rx_buf_count, DMA_FROM_DEVICE); >> + >> + tx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_tx_channel); >> + tx_param.src = t->tx_buf ? t->tx_dma : tx_reg; >> + tx_param.a_b_cnt = davinci_spi->wcount << 16 | data_type; >> + tx_param.dst = tx_reg; >> + tx_param.src_dst_bidx = t->tx_buf ? data_type : 0; >> + tx_param.link_bcntrld = 0xffff; >> + tx_param.src_dst_cidx = 0; >> + tx_param.ccnt = 1; >> + edma_write_slot(davinci_dma->dma_tx_channel, &tx_param); >> + edma_link(davinci_dma->dma_tx_channel, >> + davinci_dma->dummy_param_slot); >> + >> + rx_param.opt = TCINTEN | EDMA_TCC(davinci_dma->dma_rx_channel); >> + rx_param.src = rx_reg; >> + rx_param.a_b_cnt = davinci_spi->rcount << 16 | data_type; >> + rx_param.dst = t->rx_dma; >> + rx_param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; >> + rx_param.link_bcntrld = 0xffff; >> + rx_param.src_dst_cidx = 0; >> + rx_param.ccnt = 1; >> + edma_write_slot(davinci_dma->dma_rx_channel, &rx_param); >> + >> + iowrite16(spidat1 >> SPIDAT1_CSNR_SHIFT, >> + davinci_spi->base + SPIDAT1 + 2); >> + >> + edma_start(davinci_dma->dma_rx_channel); >> + edma_start(davinci_dma->dma_tx_channel); >> + set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); >> } >> >> - edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, >> - data_type, temp_count, 1, 0, ASYNC); >> - edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); >> - edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT); >> - edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0); >> - edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); >> - >> - if (t->rx_buf) { >> - /* initiate transaction */ >> - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); >> - >> - t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count, >> - DMA_FROM_DEVICE); >> - if (dma_mapping_error(&spi->dev, t->rx_dma)) { >> - dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", >> - count); >> - if (t->tx_buf != NULL) >> - dma_unmap_single(NULL, t->tx_dma, >> - count, DMA_TO_DEVICE); >> - return -ENOMEM; >> + /* Wait for the transfer to complete */ >> + if (spi_cfg->io_type != SPI_IO_TYPE_POLL) { >> + wait_for_completion_interruptible(&(davinci_spi->done)); >> + } else { >> + while ((davinci_spi->rcount > 0) && (ret == 0)) { >> + ret = davinci_spi_process_events(davinci_spi); >> + cpu_relax(); >> } >> - edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, >> - data_type, count, 1, 0, ASYNC); >> - edma_set_src(davinci_spi_dma->dma_rx_channel, >> - rx_reg, INCR, W8BIT); >> - edma_set_dest(davinci_spi_dma->dma_rx_channel, >> - t->rx_dma, INCR, W8BIT); >> - edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); >> - edma_set_dest_index(davinci_spi_dma->dma_rx_channel, >> - data_type, 0); >> } >> >> - if ((t->tx_buf) || (t->rx_buf)) >> - edma_start(davinci_spi_dma->dma_tx_channel); >> - >> - if (t->rx_buf) >> - edma_start(davinci_spi_dma->dma_rx_channel); >> - >> - if ((t->rx_buf) || (t->tx_buf)) >> - davinci_spi_set_dma_req(spi, 1); >> - >> - if (t->tx_buf) >> - wait_for_completion_interruptible( >> - &davinci_spi_dma->dma_tx_completion); >> - >> - if (t->rx_buf) >> - wait_for_completion_interruptible( >> - &davinci_spi_dma->dma_rx_completion); >> - >> - dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE); >> - >> - if (t->rx_buf) >> - dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE); >> - >> - /* >> - * Check for bit error, desync error,parity error,timeout error and >> - * receive overflow errors >> - */ >> - int_status = ioread32(davinci_spi->base + SPIFLG); >> + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); >> + if (spi_cfg->io_type == SPI_IO_TYPE_DMA) { >> + dma_unmap_single(NULL, t->tx_dma, tx_buf_count, >> + DMA_TO_DEVICE); >> + dma_unmap_single(NULL, t->rx_dma, rx_buf_count, >> + DMA_FROM_DEVICE); >> + } >> >> - ret = davinci_spi_check_error(davinci_spi, int_status); >> - if (ret != 0) >> - return ret; >> + clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); >> + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); >> >> - /* SPI Framework maintains the count only in bytes so convert back */ >> - davinci_spi->count *= conv; >> + if (davinci_spi->errors) { >> + ret = davinci_spi_check_error(davinci_spi, davinci_spi->errors); >> + if (ret != 0) >> + return ret; >> + } >> + if ((davinci_spi->rcount != 0) || (davinci_spi->wcount != 0)) { >> + sdev = davinci_spi->bitbang.master->dev.parent; >> + dev_info(sdev, "SPI data transfer error\n"); >> + return -EIO; >> + } >> >> return t->len; >> } >> >> /** >> - * davinci_spi_irq - IRQ handler for DaVinci SPI >> + * davinci_spi_irq - probe function for SPI Master Controller > > This doesn't look right. > >> * @irq: IRQ number for this SPI Master >> * @context_data: structure for SPI Master controller davinci_spi >> + * >> + * ISR will determine that interrupt arrives either for READ or WRITE command. >> + * According to command it will do the appropriate action. It will check >> + * transfer length and if it is not zero then dispatch transfer command again. >> + * If transfer length is zero then it will indicate the COMPLETION so that >> + * davinci_spi_bufs function can go ahead. >> */ >> static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) >> { >> struct davinci_spi *davinci_spi = context_data; >> - u32 int_status, rx_data = 0; >> - irqreturn_t ret = IRQ_NONE; >> + int status; >> >> - int_status = ioread32(davinci_spi->base + SPIFLG); >> + status = davinci_spi_process_events(davinci_spi); >> + if (unlikely(status != 0)) >> + clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); >> >> - while ((int_status & SPIFLG_RX_INTR_MASK)) { >> - if (likely(int_status & SPIFLG_RX_INTR_MASK)) { >> - ret = IRQ_HANDLED; >> + if ((davinci_spi->rcount == 0) || (status != 0)) >> + complete(&(davinci_spi->done)); >> >> - rx_data = ioread32(davinci_spi->base + SPIBUF); >> - davinci_spi->get_rx(rx_data, davinci_spi); >> + return IRQ_HANDLED; >> +} >> >> - /* Disable Receive Interrupt */ >> - iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR), >> - davinci_spi->base + SPIINT); >> - } else >> - (void)davinci_spi_check_error(davinci_spi, int_status); >> +resource_size_t davinci_spi_get_dma_by_index(struct platform_device *dev, >> + unsigned long index) >> +{ >> + struct resource *r; >> >> - int_status = ioread32(davinci_spi->base + SPIFLG); >> - } >> + r = platform_get_resource(dev, IORESOURCE_DMA, index); >> + if (r != NULL) >> + return r->start; >> >> - return ret; >> + return SPI_NO_RESOURCE; >> } >> >> /** >> * davinci_spi_probe - probe function for SPI Master Controller >> * @pdev: platform_device structure which contains plateform specific data >> + * >> + * According to Linux Device Model this function will be invoked by Linux >> + * with platform_device struct which contains the device specific info. >> + * This function will map the SPI controller's memory, register IRQ, >> + * Reset SPI controller and setting its registers to default value. >> + * It will invoke spi_bitbang_start to create work queue so that client driver >> + * can register transfer method to work queue. > > Another candidate; improve documentation > >> */ >> static int davinci_spi_probe(struct platform_device *pdev) >> { >> @@ -1020,6 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev) >> resource_size_t dma_tx_chan = SPI_NO_RESOURCE; >> resource_size_t dma_eventq = SPI_NO_RESOURCE; >> int i = 0, ret = 0; >> + u32 spipc0; >> >> pdata = pdev->dev.platform_data; >> if (pdata == NULL) { >> @@ -1071,10 +939,12 @@ static int davinci_spi_probe(struct platform_device *pdev) >> goto unmap_io; >> } >> >> - ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, >> + ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, >> dev_name(&pdev->dev), davinci_spi); >> - if (ret) >> + if (ret != 0) { >> + ret = -EAGAIN; >> goto unmap_io; >> + } >> >> /* Allocate tmp_buf for tx_buf */ >> davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); >> @@ -1104,55 +974,23 @@ static int davinci_spi_probe(struct platform_device *pdev) >> >> davinci_spi->bitbang.chipselect = davinci_spi_chipselect; >> davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; >> + davinci_spi->bitbang.txrx_bufs = davinci_spi_txrx_bufs; >> >> davinci_spi->version = pdata->version; >> - use_dma = pdata->use_dma; >> >> davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; >> if (davinci_spi->version == SPI_VERSION_2) >> davinci_spi->bitbang.flags |= SPI_READY; >> >> - if (use_dma) { >> - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); >> - if (r) >> - dma_rx_chan = r->start; >> - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); >> - if (r) >> - dma_tx_chan = r->start; >> - r = platform_get_resource(pdev, IORESOURCE_DMA, 2); >> - if (r) >> - dma_eventq = r->start; >> - } >> - >> - if (!use_dma || >> - dma_rx_chan == SPI_NO_RESOURCE || >> - dma_tx_chan == SPI_NO_RESOURCE || >> - dma_eventq == SPI_NO_RESOURCE) { >> - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; >> - use_dma = 0; >> - } else { >> - davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; >> - davinci_spi->dma_channels = kzalloc(master->num_chipselect >> - * sizeof(struct davinci_spi_dma), GFP_KERNEL); >> - if (davinci_spi->dma_channels == NULL) { >> - ret = -ENOMEM; >> - goto free_clk; >> - } >> - >> - for (i = 0; i < master->num_chipselect; i++) { >> - davinci_spi->dma_channels[i].dma_rx_channel = -1; >> - davinci_spi->dma_channels[i].dma_rx_sync_dev = >> - dma_rx_chan; >> - davinci_spi->dma_channels[i].dma_tx_channel = -1; >> - davinci_spi->dma_channels[i].dma_tx_sync_dev = >> - dma_tx_chan; >> - davinci_spi->dma_channels[i].eventq = dma_eventq; >> - } >> - dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" >> - "Using RX channel = %d , TX channel = %d and " >> - "event queue = %d", dma_rx_chan, dma_tx_chan, >> - dma_eventq); >> - } >> + dma_rx_chan = davinci_spi_get_dma_by_index(pdev, RX_DMA_INDEX); >> + dma_tx_chan = davinci_spi_get_dma_by_index(pdev, TX_DMA_INDEX); >> + dma_eventq = davinci_spi_get_dma_by_index(pdev, EVENTQ_DMA_INDEX); >> + davinci_spi->dma_channels.dma_rx_channel = -1; >> + davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; >> + davinci_spi->dma_channels.dma_tx_channel = -1; >> + davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; >> + davinci_spi->dma_channels.dummy_param_slot = -1; >> + davinci_spi->dma_channels.eventq = dma_eventq; >> >> davinci_spi->get_rx = davinci_spi_rx_buf_u8; >> davinci_spi->get_tx = davinci_spi_tx_buf_u8; >> @@ -1164,31 +1002,28 @@ static int davinci_spi_probe(struct platform_device *pdev) >> udelay(100); >> iowrite32(1, davinci_spi->base + SPIGCR0); >> >> - /* Clock internal */ >> - if (davinci_spi->pdata->clk_internal) >> - set_io_bits(davinci_spi->base + SPIGCR1, >> - SPIGCR1_CLKMOD_MASK); >> - else >> - clear_io_bits(davinci_spi->base + SPIGCR1, >> - SPIGCR1_CLKMOD_MASK); >> + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ >> + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; >> + iowrite32(spipc0, davinci_spi->base + SPIPC0); >> >> - /* master mode default */ >> - set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); >> + /* initialize chip selects */ >> + if (pdata->chip_sel != NULL) { >> + for (i = 0; i < pdata->num_chipselect; i++) { >> + if (pdata->chip_sel[i] != SPI_INTERN_CS) >> + gpio_direction_output(pdata->chip_sel[i], 1); >> + } >> + } >> + iowrite32(SPIDEF_CSDEF_MASK, davinci_spi->base + SPIDEF); >> >> - if (davinci_spi->pdata->intr_level) >> - iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); >> - else >> - iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); >> + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); >> + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); >> + set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); >> >> ret = spi_bitbang_start(&davinci_spi->bitbang); >> - if (ret) >> + if (ret != 0) >> goto free_clk; >> >> - dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); >> - >> - if (!pdata->poll_mode) >> - dev_info(&pdev->dev, "Operating in interrupt mode" >> - " using IRQ %d\n", davinci_spi->irq); >> + dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); >> >> return ret; >> >> @@ -1220,7 +1055,7 @@ err: >> * It will also call spi_bitbang_stop to destroy the work queue which was >> * created by spi_bitbang_start. >> */ >> -static int __exit davinci_spi_remove(struct platform_device *pdev) >> +static int __devexit davinci_spi_remove(struct platform_device *pdev) >> { >> struct davinci_spi *davinci_spi; >> struct spi_master *master; >> @@ -1242,8 +1077,11 @@ static int __exit davinci_spi_remove(struct platform_device *pdev) >> } >> >> static struct platform_driver davinci_spi_driver = { >> - .driver.name = "spi_davinci", >> - .remove = __exit_p(davinci_spi_remove), >> + .driver = { >> + .name = "spi_davinci", >> + .owner = THIS_MODULE, >> + }, >> + .remove = __devexit_p(davinci_spi_remove), >> }; > > Another candidate. Corrections to platform_driver structure and > __devexit annotations. > >> >> static int __init davinci_spi_init(void) >> -- >> 1.6.3.3 >> >> > > > > -- > Grant Likely, B.Sc., P.Eng. > Secret Lab Technologies Ltd. > ------------------------------------------------------------------------------ The Palm PDK Hot Apps Program offers developers who use the Plug-In Development Kit to bring their C/C++ apps to Palm for a share of $1 Million in cash or HP Products. Visit us here for more details: http://p.sf.net/sfu/dev2dev-palm ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2010-08-02 15:53 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E7ED0A13-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2010-08-03 7:33 ` Grant Likely 2010-08-03 7:55 ` Christophe Aeschlimann 2 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-08-02 15:53 UTC (permalink / raw) To: Brian Niebuhr, Grant Likely Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org Hi Brian, On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: > Grant - > > For my part, I've already sunk way more time into this than I ever > intended, and I really have no clue how to break this patch down into > smaller patches. I don't really care much if the patch gets accepted > or not - I am just trying to help out all of the other users that are > stuck with a broken driver like I was. Maybe if TI wants to give > their customers a driver that actually works they'll pick it up and do > the rest of the work that's necessary to get it accepted. Thanks for all the work on this so far. We will work on breaking this patch up and getting the fixes accepted upstream. Regards, Sekhar ------------------------------------------------------------------------------ The Palm PDK Hot Apps Program offers developers who use the Plug-In Development Kit to bring their C/C++ apps to Palm for a share of $1 Million in cash or HP Products. Visit us here for more details: http://p.sf.net/sfu/dev2dev-palm ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <B85A65D85D7EB246BE421B3FB0FBB59301E7ED0A13-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E7ED0A13-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-08-20 11:06 ` Caglar Akyuz [not found] ` <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Caglar Akyuz @ 2010-08-20 11:06 UTC (permalink / raw) To: Nori, Sekhar Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, Brian Niebuhr On Monday 02 August 2010 06:53:16 pm Nori, Sekhar wrote: > Hi Brian, > > On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: > > Grant - > > > > > > For my part, I've already sunk way more time into this than I ever > > intended, and I really have no clue how to break this patch down into > > smaller patches. I don't really care much if the patch gets accepted > > or not - I am just trying to help out all of the other users that are > > stuck with a broken driver like I was. Maybe if TI wants to give > > their customers a driver that actually works they'll pick it up and do > > the rest of the work that's necessary to get it accepted. > > Thanks for all the work on this so far. We will work on breaking > this patch up and getting the fixes accepted upstream. > Is there any improvement on this or anybody is actively working on submitting patches? I'm going to try this driver on DaVinci DM6446 and OMAP L-138 with different peripherals. If nobody is expected to submit something soon, then I can work on preparing incremental patches while working with the driver. I can start sending patches next week or so. Best Regards, Caglar > Regards, > Sekhar > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2010-08-20 14:46 ` Todd Fischer 2010-08-20 17:19 ` Grant Likely 2010-08-23 4:28 ` Nori, Sekhar 2 siblings, 0 replies; 33+ messages in thread From: Todd Fischer @ 2010-08-20 14:46 UTC (permalink / raw) To: Caglar Akyuz Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, Brian Niebuhr [-- Attachment #1.1: Type: text/plain, Size: 1902 bytes --] On Fri, 2010-08-20 at 14:06 +0300, Caglar Akyuz wrote: > On Monday 02 August 2010 06:53:16 pm Nori, Sekhar wrote: > > Hi Brian, > > > > On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: > > > Grant - > > > > > > > > > For my part, I've already sunk way more time into this than I ever > > > intended, and I really have no clue how to break this patch down into > > > smaller patches. I don't really care much if the patch gets accepted > > > or not - I am just trying to help out all of the other users that are > > > stuck with a broken driver like I was. Maybe if TI wants to give > > > their customers a driver that actually works they'll pick it up and do > > > the rest of the work that's necessary to get it accepted. > > > > Thanks for all the work on this so far. We will work on breaking > > this patch up and getting the fixes accepted upstream. > > > > Is there any improvement on this or anybody is actively working on submitting > patches? > > I'm going to try this driver on DaVinci DM6446 and OMAP L-138 with different > peripherals. If nobody is expected to submit something soon, then I can work > on preparing incremental patches while working with the driver. I can start > sending patches next week or so. Caglar, I will be using Brian's driver on DM365. I will let you know if I encounter any issues. Todd > Best Regards, > Caglar > > > Regards, > > Sekhar > > _______________________________________________ > > Davinci-linux-open-source mailing list > > Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source [-- Attachment #1.2: Type: text/html, Size: 2655 bytes --] [-- Attachment #2: Type: text/plain, Size: 0 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2010-08-20 14:46 ` Todd Fischer @ 2010-08-20 17:19 ` Grant Likely 2010-08-23 4:28 ` Nori, Sekhar 2 siblings, 0 replies; 33+ messages in thread From: Grant Likely @ 2010-08-20 17:19 UTC (permalink / raw) To: Caglar Akyuz Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/, Nori, Sekhar, Brian Niebuhr On Fri, Aug 20, 2010 at 5:06 AM, Caglar Akyuz <caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Monday 02 August 2010 06:53:16 pm Nori, Sekhar wrote: >> Hi Brian, >> >> On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: >> > Grant - >> > >> > >> > For my part, I've already sunk way more time into this than I ever >> > intended, and I really have no clue how to break this patch down into >> > smaller patches. I don't really care much if the patch gets accepted >> > or not - I am just trying to help out all of the other users that are >> > stuck with a broken driver like I was. Maybe if TI wants to give >> > their customers a driver that actually works they'll pick it up and do >> > the rest of the work that's necessary to get it accepted. >> >> Thanks for all the work on this so far. We will work on breaking >> this patch up and getting the fixes accepted upstream. >> > > Is there any improvement on this or anybody is actively working on submitting > patches? > > I'm going to try this driver on DaVinci DM6446 and OMAP L-138 with different > peripherals. If nobody is expected to submit something soon, then I can work > on preparing incremental patches while working with the driver. I can start > sending patches next week or so. > > Best Regards, > Caglar Thanks Caglar for picking up this work. I look forward to seeing the patches. Let me know if you need any help with getting them in shape for merging. g. ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2010-08-20 14:46 ` Todd Fischer 2010-08-20 17:19 ` Grant Likely @ 2010-08-23 4:28 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350B45-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-08-23 4:28 UTC (permalink / raw) To: Caglar Akyuz Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr Hi Caglar, On Fri, Aug 20, 2010 at 16:36:33, Caglar Akyuz wrote: > On Monday 02 August 2010 06:53:16 pm Nori, Sekhar wrote: > > Hi Brian, > > > > On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: > > > Grant - > > > > > > > > > For my part, I've already sunk way more time into this than I ever > > > intended, and I really have no clue how to break this patch down into > > > smaller patches. I don't really care much if the patch gets accepted > > > or not - I am just trying to help out all of the other users that are > > > stuck with a broken driver like I was. Maybe if TI wants to give > > > their customers a driver that actually works they'll pick it up and do > > > the rest of the work that's necessary to get it accepted. > > > > Thanks for all the work on this so far. We will work on breaking > > this patch up and getting the fixes accepted upstream. > > > > Is there any improvement on this or anybody is actively working on submitting > patches? > > I'm going to try this driver on DaVinci DM6446 and OMAP L-138 with different > peripherals. If nobody is expected to submit something soon, then I can work > on preparing incremental patches while working with the driver. I can start > sending patches next week or so. I have been spending time on this (admittedly on and off) since I wrote that email and have broken down the work into ~20 patches so far. Starting to scratch the DMA related changes right now. So, I guess I am somewhere midway. I pushed a branch containing the work so far here: http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite This isn't tested or submit-worthy yet. I was hoping to break down the complete work, test it and get reviewed by Brian. Also, the final work may differ from Brian's work slightly as I did some improvements while I was the fat patch breaking down. The breakdown wasn't mechanical because Brian's improvements are very intertwined and if I just simply 'selected hunks' it wouldn't make for a very reviewable patch series. Have you also been parallely working on this? If not, I hope you can start from what I have already completed. I will continue to work on it anyway. This way hopefully the patch series should be ready sooner. Thanks, Sekhar ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350B45-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-08-23 4:40 ` Grant Likely 2010-08-23 8:54 ` Caglar Akyuz 1 sibling, 0 replies; 33+ messages in thread From: Grant Likely @ 2010-08-23 4:40 UTC (permalink / raw) To: Nori, Sekhar, Caglar Akyuz Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr "Nori, Sekhar" <nsekhar-l0cyMroinI0@public.gmane.org> wrote: >Hi Caglar, > >On Fri, Aug 20, 2010 at 16:36:33, Caglar Akyuz wrote: >> On Monday 02 August 2010 06:53:16 pm Nori, Sekhar wrote: >> > Hi Brian, >> > >> > On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote: >> > > Grant - >> > > >> > > >> > > For my part, I've already sunk way more time into this than I ever >> > > intended, and I really have no clue how to break this patch down into >> > > smaller patches. I don't really care much if the patch gets accepted >> > > or not - I am just trying to help out all of the other users that are >> > > stuck with a broken driver like I was. Maybe if TI wants to give >> > > their customers a driver that actually works they'll pick it up and do >> > > the rest of the work that's necessary to get it accepted. >> > >> > Thanks for all the work on this so far. We will work on breaking >> > this patch up and getting the fixes accepted upstream. >> > >> >> Is there any improvement on this or anybody is actively working on submitting >> patches? >> >> I'm going to try this driver on DaVinci DM6446 and OMAP L-138 with different >> peripherals. If nobody is expected to submit something soon, then I can work >> on preparing incremental patches while working with the driver. I can start >> sending patches next week or so. > >I have been spending time on this (admittedly on and off) since I wrote that >email and have broken down the work into ~20 patches so far. Starting to >scratch the DMA related changes right now. So, I guess I am somewhere midway. > >I pushed a branch containing the work so far here: > >http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite I like what I see so far. Feel free to post subsets of the whole series as soon as you feel they are ready so I can start adding bits to my next-door branch. g. -- Sent from my Android phone with K-9 Mail. Please excuse my brevity. ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350B45-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2010-08-23 4:40 ` Grant Likely @ 2010-08-23 8:54 ` Caglar Akyuz [not found] ` <201008231154.10411.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 1 sibling, 1 reply; 33+ messages in thread From: Caglar Akyuz @ 2010-08-23 8:54 UTC (permalink / raw) To: Nori, Sekhar Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr On Monday 23 August 2010 07:28:48 am Nori, Sekhar wrote: > Hi Caglar, > Hi, [...] > I have been spending time on this (admittedly on and off) since I wrote > that email and have broken down the work into ~20 patches so far. Starting > to scratch the DMA related changes right now. So, I guess I am somewhere > midway. > > I pushed a branch containing the work so far here: > > http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=ref > s/heads/davinci-spi-rewrite > This is great. > This isn't tested or submit-worthy yet. I was hoping to break down the > complete work, test it and get reviewed by Brian. Also, the final work > may differ from Brian's work slightly as I did some improvements while > I was the fat patch breaking down. > > The breakdown wasn't mechanical because Brian's improvements are very > intertwined and if I just simply 'selected hunks' it wouldn't make for > a very reviewable patch series. > I was hoping to reach to an exact copy of Brian's version since that version is tested by Brian and some others. but if you say so... > Have you also been parallely working on this? If not, I hope you can start > from what I have already completed. I will continue to work on it anyway. > This way hopefully the patch series should be ready sooner. > I'll start this week working on this, so your patches are perfect for me. I don't want to interrupt your working process, I'll follow your tree closely for your in-coming changes. Regards, Caglar > Thanks, > Sekhar > ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <201008231154.10411.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2010-08-23 9:30 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350E47-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-08-23 9:30 UTC (permalink / raw) To: Caglar Akyuz Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr On Mon, Aug 23, 2010 at 14:24:10, Caglar Akyuz wrote: > On Monday 23 August 2010 07:28:48 am Nori, Sekhar wrote: > > Hi Caglar, > > > > Hi, > > [...] > > > I have been spending time on this (admittedly on and off) since I wrote > > that email and have broken down the work into ~20 patches so far. Starting > > to scratch the DMA related changes right now. So, I guess I am somewhere > > midway. > > > > I pushed a branch containing the work so far here: > > > > http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=ref > > s/heads/davinci-spi-rewrite > > > > This is great. > > > This isn't tested or submit-worthy yet. I was hoping to break down the > > complete work, test it and get reviewed by Brian. Also, the final work > > may differ from Brian's work slightly as I did some improvements while > > I was the fat patch breaking down. > > > > The breakdown wasn't mechanical because Brian's improvements are very > > intertwined and if I just simply 'selected hunks' it wouldn't make for > > a very reviewable patch series. > > > > I was hoping to reach to an exact copy of Brian's version since that version > is tested by Brian and some others. but if you say so... Yeah, that was my initial goal too. Anyway, at the end of it we can review the delta separately and make sure the changes are worth making and don't actually break functionality. Thanks, Sekhar ------------------------------------------------------------------------------ This SF.net email is sponsored by Make an app they can't live without Enter the BlackBerry Developer Challenge http://p.sf.net/sfu/RIM-dev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350E47-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-09-13 23:45 ` Michael Williamson [not found] ` <4C8EB795.1080607-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-09-13 23:45 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org Hi Sekhar, On 08/23/2010 05:30 AM, Nori, Sekhar wrote: > On Mon, Aug 23, 2010 at 14:24:10, Caglar Akyuz wrote: >> On Monday 23 August 2010 07:28:48 am Nori, Sekhar wrote: >>> Hi Caglar, >>> >> >> Hi, >> >> [...] >> >>> I have been spending time on this (admittedly on and off) since I wrote >>> that email and have broken down the work into ~20 patches so far. Starting >>> to scratch the DMA related changes right now. So, I guess I am somewhere >>> midway. >>> >>> I pushed a branch containing the work so far here: >>> >>> http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=ref >>> s/heads/davinci-spi-rewrite >>> >> I've been trying to take a peek, but the arago site seems to be flakey lately, giving a lot of messages like the one below. Not sure if you are aware of this. Looking forward to seeing this... Thanks! -Mike (Arago Error Message). XML Parsing Error: undefined entity Location: http://arago-project.org/git/projects/?p=linux-davinci.git;a=summary Line Number 41, Column 20:<div class="title"> </div> -------------------^ ^ permalink raw reply [flat|nested] 33+ messages in thread
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* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C8EB795.1080607-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-09-14 5:43 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4C95-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-09-14 5:43 UTC (permalink / raw) To: Michael Williamson Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org On Tue, Sep 14, 2010 at 05:15:25, Michael Williamson wrote: > Hi Sekhar, > > On 08/23/2010 05:30 AM, Nori, Sekhar wrote: > > On Mon, Aug 23, 2010 at 14:24:10, Caglar Akyuz wrote: > >> On Monday 23 August 2010 07:28:48 am Nori, Sekhar wrote: > >>> Hi Caglar, > >>> > >> > >> Hi, > >> > >> [...] > >> > >>> I have been spending time on this (admittedly on and off) since I wrote > >>> that email and have broken down the work into ~20 patches so far. Starting > >>> to scratch the DMA related changes right now. So, I guess I am somewhere > >>> midway. > >>> > >>> I pushed a branch containing the work so far here: > >>> > >>> http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=ref > >>> s/heads/davinci-spi-rewrite > >>> > >> > > I've been trying to take a peek, but the arago site seems to be flakey lately, > giving a lot of messages like the one below. Not sure if you are aware of this. Hmm, I have seen this kind of error in the past, but not lately. Accessed the site just now without issues. > Looking forward to seeing this... Thanks! Got side-tracked the last two weeks. The DMA changes are the major chunk left. Hopefully will have the final patch set ready with little more effort. Thanks, Sekhar ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4C95-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-09-14 6:04 ` Caglar Akyuz [not found] ` <201009140904.59555.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Caglar Akyuz @ 2010-09-14 6:04 UTC (permalink / raw) To: davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org On Tuesday 14 September 2010 08:43:41 am Nori, Sekhar wrote: > On Tue, Sep 14, 2010 at 05:15:25, Michael Williamson wrote: > > Hi Sekhar, > > > > On 08/23/2010 05:30 AM, Nori, Sekhar wrote: > > > On Mon, Aug 23, 2010 at 14:24:10, Caglar Akyuz wrote: > > >> On Monday 23 August 2010 07:28:48 am Nori, Sekhar wrote: > > >>> Hi Caglar, > > >> > > >> Hi, > > >> > > >> [...] > > >> > > >>> I have been spending time on this (admittedly on and off) since I > > >>> wrote that email and have broken down the work into ~20 patches so > > >>> far. Starting to scratch the DMA related changes right now. So, I > > >>> guess I am somewhere midway. > > >>> > > >>> I pushed a branch containing the work so far here: > > >>> > > >>> http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog > > >>>;h=ref s/heads/davinci-spi-rewrite > > > > I've been trying to take a peek, but the arago site seems to be flakey > > lately, giving a lot of messages like the one below. Not sure if you are > > aware of this. > > Hmm, I have seen this kind of error in the past, but not lately. Accessed > the site just now without issues. > > > Looking forward to seeing this... Thanks! > > Got side-tracked the last two weeks. The DMA changes are the major > chunk left. Hopefully will have the final patch set ready with > little more effort. > Yes, your patches seems ok and mostly complete. I'm waiting for hardware to test those, will let you know when I do some testing. Regards, Caglar > Thanks, > Sekhar > > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source > ^ permalink raw reply [flat|nested] 33+ messages in thread
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* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <201009140904.59555.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2010-09-14 7:14 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4D9B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-09-14 7:14 UTC (permalink / raw) To: Caglar Akyuz, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org On Tue, Sep 14, 2010 at 11:34:59, Caglar Akyuz wrote: > Yes, your patches seems ok and mostly complete. I'm waiting for hardware to > test those, will let you know when I do some testing. Thanks! To save time, I haven't tested these patches myself. I have only made sure individual patches don't break the build. Was planning to test after the complete series is ready. Regards, Sekhar ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4D9B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-09-14 13:10 ` Michael Williamson [not found] ` <4C8F7460.6050006-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-09-14 13:10 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org On 9/14/2010 3:14 AM, Nori, Sekhar wrote: > On Tue, Sep 14, 2010 at 11:34:59, Caglar Akyuz wrote: > >> Yes, your patches seems ok and mostly complete. I'm waiting for hardware to >> test those, will let you know when I do some testing. > > Thanks! To save time, I haven't tested these patches myself. I have only made > sure individual patches don't break the build. Was planning to test after > the complete series is ready. > If it would help, If there are portions of the patch set that can be tested with DMA disabled or something, I'd be willing to kick the tires. I have da850 hardware available. -Mike ^ permalink raw reply [flat|nested] 33+ messages in thread
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* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C8F7460.6050006-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-09-14 13:26 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF50C1-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-09-14 13:26 UTC (permalink / raw) To: Michael Williamson Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org Hi Mike, On Tue, Sep 14, 2010 at 18:40:56, Michael Williamson wrote: > On 9/14/2010 3:14 AM, Nori, Sekhar wrote: > > > On Tue, Sep 14, 2010 at 11:34:59, Caglar Akyuz wrote: > > > >> Yes, your patches seems ok and mostly complete. I'm waiting for hardware to > >> test those, will let you know when I do some testing. > > > > Thanks! To save time, I haven't tested these patches myself. I have only made > > sure individual patches don't break the build. Was planning to test after > > the complete series is ready. > > > > > If it would help, If there are portions of the patch set that can be tested > with DMA disabled or something, I'd be willing to kick the tires. I have > da850 hardware available. Thanks for being brave and offering to help! Yes, interrupt and polled mode can be tried. Since a lot of testing has already happened on the original patch, I was planning to test the series only after it is complete. Any issues found can be narrowed down to the differences (which I hope will be justifiable). Thanks, Sekhar ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF50C1-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-09-18 13:08 ` Michael Williamson [not found] ` <4C94B9BD.4010606-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-09-18 13:08 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org On 09/14/2010 09:26 AM, Nori, Sekhar wrote: > Hi Mike, > > On Tue, Sep 14, 2010 at 18:40:56, Michael Williamson wrote: >> On 9/14/2010 3:14 AM, Nori, Sekhar wrote: >> >>> On Tue, Sep 14, 2010 at 11:34:59, Caglar Akyuz wrote: >>> >>>> Yes, your patches seems ok and mostly complete. I'm waiting for hardware to >>>> test those, will let you know when I do some testing. >>> >>> Thanks! To save time, I haven't tested these patches myself. I have only made >>> sure individual patches don't break the build. Was planning to test after >>> the complete series is ready. >>> >> >> >> If it would help, If there are portions of the patch set that can be tested >> with DMA disabled or something, I'd be willing to kick the tires. I have >> da850 hardware available. > > Thanks for being brave and offering to help! Yes, interrupt and polled mode > can be tried. Since a lot of testing has already happened on the original patch, > I was planning to test the series only after it is complete. Any issues found can > be narrowed down to the differences (which I hope will be justifiable). > > Thanks, > Sekhar So I am testing with a configuration which is pretty much the same as the da850 EVM; a SPI-NOR flash on the first chip select of SPI1. Both poll and interrupt modes work. So far so good, and Brian's work really sorted out a bunch of questions I had looking at the original spi code. Nice work, Nori, for break the patch into logical blocks. I do have a couple of comments: * I'm not sure I understand why there is a "intr_line" field in the platform data and then a possibility to configure an "io_type" as interrupt or polled at the chip select level. I got burned by setting the "io_type" to SPI_IO_TYPE_INTR and not setting "intr_line" to non-zero. The probe just hung because it was trying to use interrupts but never setting SPILVL register. These fields aren't mutually exclusive. Is the intent to support a configuration with one chip select running in polled mode and another in interrupt mode? If so, then it seems the SPILVL register logic needs some attention during each transfer. * As a (novice) user, I'd really like to see some comments / hints added to the ../mach-davinci/include/mach/spi.h file to describe how all of the platform fields should be set. Some of the fields aren't very obvious as to how to initialize them without having a data sheet on one screen and plowing through the driver on another. This might have cleaned up my confusion on the first item. Looking forward to seeing this moving into the mainline. Thanks! -Mike ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C94B9BD.4010606-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-09-18 13:16 ` Michael Williamson 2010-09-20 15:08 ` Nori, Sekhar 1 sibling, 0 replies; 33+ messages in thread From: Michael Williamson @ 2010-09-18 13:16 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org [...] > I had looking at the original spi code. Nice work, Nori, for break the patch s/Nori/Sekhar Sorry about that, Sekhar. -Mike ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C94B9BD.4010606-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 2010-09-18 13:16 ` Michael Williamson @ 2010-09-20 15:08 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6F5385B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 1 sibling, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-09-20 15:08 UTC (permalink / raw) To: Michael Williamson Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Caglar Akyuz Hi Michael, On Sat, Sep 18, 2010 at 18:38:13, Michael Williamson wrote: > On 09/14/2010 09:26 AM, Nori, Sekhar wrote: > > Hi Mike, > > > > On Tue, Sep 14, 2010 at 18:40:56, Michael Williamson wrote: > >> On 9/14/2010 3:14 AM, Nori, Sekhar wrote: > >> > >>> On Tue, Sep 14, 2010 at 11:34:59, Caglar Akyuz wrote: > >>> > >>>> Yes, your patches seems ok and mostly complete. I'm waiting for hardware to > >>>> test those, will let you know when I do some testing. > >>> > >>> Thanks! To save time, I haven't tested these patches myself. I have only made > >>> sure individual patches don't break the build. Was planning to test after > >>> the complete series is ready. > >>> > >> > >> > >> If it would help, If there are portions of the patch set that can be tested > >> with DMA disabled or something, I'd be willing to kick the tires. I have > >> da850 hardware available. > > > > Thanks for being brave and offering to help! Yes, interrupt and polled mode > > can be tried. Since a lot of testing has already happened on the original patch, > > I was planning to test the series only after it is complete. Any issues found can > > be narrowed down to the differences (which I hope will be justifiable). > > > > Thanks, > > Sekhar > > So I am testing with a configuration which is pretty much the same as the da850 EVM; > a SPI-NOR flash on the first chip select of SPI1. Both poll and interrupt modes > work. So far so good, and Brian's work really sorted out a bunch of questions > I had looking at the original spi code. Nice work, Nori, for break the patch > into logical blocks. I do have a couple of comments: Really?? Just worked? Wooohooo... > > * I'm not sure I understand why there is a "intr_line" field in the platform > data and then a possibility to configure an "io_type" as interrupt or polled at > the chip select level. I got burned by setting the "io_type" to SPI_IO_TYPE_INTR > and not setting "intr_line" to non-zero. The probe just hung because it was > trying to use interrupts but never setting SPILVL register. These fields aren't > mutually exclusive. Is the intent to support a configuration with one chip select > running in polled mode and another in interrupt mode? If so, then it seems the SPILVL > register logic needs some attention during each transfer. The intr_line to be set is constant for the SoC. So, irrespective of what the individual devices on a given board choose to operate (interrupted, polled or DMA) the SoC code (da850.c) should setup the intr_line according to how the SPI interrupt is wired within the SoC. Can you clarify what you mean by "needs some attention during each transfer"? > > * As a (novice) user, I'd really like to see some comments / hints added to the > ../mach-davinci/include/mach/spi.h file to describe how all of the platform fields > should be set. Some of the fields aren't very obvious as to how to initialize > them without having a data sheet on one screen and plowing through the > driver on another. This might have cleaned up my confusion on the first item. Good point. Will ensure this. Thanks, Sekhar ------------------------------------------------------------------------------ Start uncovering the many advantages of virtual appliances and start using them to simplify application deployment and accelerate your shift to cloud computing. http://p.sf.net/sfu/novell-sfdev2dev ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6F5385B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-09-20 17:42 ` Michael Williamson [not found] ` <4C979D1D.1070707-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-09-20 17:42 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org On 9/20/2010 11:08 AM, Nori, Sekhar wrote: > Hi Michael, > > On Sat, Sep 18, 2010 at 18:38:13, Michael Williamson wrote: >> >> * I'm not sure I understand why there is a "intr_line" field in the platform >> data and then a possibility to configure an "io_type" as interrupt or polled at >> the chip select level. I got burned by setting the "io_type" to SPI_IO_TYPE_INTR >> and not setting "intr_line" to non-zero. The probe just hung because it was >> trying to use interrupts but never setting SPILVL register. These fields aren't >> mutually exclusive. Is the intent to support a configuration with one chip select >> running in polled mode and another in interrupt mode? If so, then it seems the SPILVL >> register logic needs some attention during each transfer. > > The intr_line to be set is constant for the SoC. So, irrespective of what the > individual devices on a given board choose to operate (interrupted, polled or DMA) > the SoC code (da850.c) should setup the intr_line according to how the SPI interrupt > is wired within the SoC. Can you clarify what you mean by "needs some attention during > each transfer"? > Ah... OK. Thank you. I now see that the SPILVL can be INT0 or INT1 for other davinci SoCs like the DM644x. For the da850 (OMAP-L138), SPILVL is valid only for INT1. So pretty much, if your using a da850 (at least), intr_line has to be 1. On other platforms, it carries a lot more meaning... Please ignore my ignorance... Let me know if you want testing on the DMA portion of the patch (when your ready, of course). -Mike ^ permalink raw reply [flat|nested] 33+ messages in thread
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* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C979D1D.1070707-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-09-27 17:35 ` Nori, Sekhar 2010-10-06 15:37 ` Nori, Sekhar 1 sibling, 0 replies; 33+ messages in thread From: Nori, Sekhar @ 2010-09-27 17:35 UTC (permalink / raw) To: Michael Williamson Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org Hi Mike, On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: > > Let me know if you want testing on the DMA portion of the patch (when your ready, of course). > I just got back to this last Friday. Will let you know once done. Meanwhile I added your Tested-By: to the existing patches. Thanks for testing. Regards, Sekhar ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4C979D1D.1070707-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 2010-09-27 17:35 ` Nori, Sekhar @ 2010-10-06 15:37 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302342050C7-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 1 sibling, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-10-06 15:37 UTC (permalink / raw) To: Michael Williamson Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr, Caglar Akyuz Hi Mike, On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: > > Let me know if you want testing on the DMA portion of the patch (when your ready, of course). I just finished pushing the DMA related patches to the git branch[1]. I have not tested yet, but feel free to give it a go (maybe I will get lucky again!). Also, do you have patches adding SPI support for DA850 platform? I can include these patches on this branch so others who will be testing don’t have to repeat the work. Thanks, Sekhar [1] http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite ------------------------------------------------------------------------------ Beautiful is writing same markup. Internet Explorer 9 supports standards for HTML5, CSS3, SVG 1.1, ECMAScript5, and DOM L2 & L3. Spend less time writing and rewriting code and more time creating great experiences on the web. Be a part of the beta today. http://p.sf.net/sfu/beautyoftheweb _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302342050C7-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-10-07 3:55 ` Michael Williamson 2010-10-08 19:22 ` Michael Williamson 1 sibling, 0 replies; 33+ messages in thread From: Michael Williamson @ 2010-10-07 3:55 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr Hi Sekhar, On 10/06/2010 11:37 AM, Nori, Sekhar wrote: > Hi Mike, > > On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: >> >> Let me know if you want testing on the DMA portion of the patch (when your ready, of course). > > I just finished pushing the DMA related patches to the git branch[1]. > I have not tested yet, but feel free to give it a go (maybe I will get > lucky again!). > > Also, do you have patches adding SPI support for DA850 platform? > I can include these patches on this branch so others who will be > testing don’t have to repeat the work. > > Thanks, > Sekhar > > [1] http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite > Great news. I'll try to give it a spin before the weekend. I do have a patch for the MityDSP-L138 (da850 based), I could propose a patch set for the da850-evm (both use the same SPI-NOR device, same SPI port and chip select). I need to separate it out from some other work, and I'm a little bleary eyed right now. It's pretty straightforward, though. We've also got a couple of other devices that we can tinker with as well (a couple of different SPI/CAN interface chips). I'll let you know what we find. Thanks for hammering this out. -Mike _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302342050C7-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2010-10-07 3:55 ` Michael Williamson @ 2010-10-08 19:22 ` Michael Williamson [not found] ` <4CAF6F86.40201-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 1 sibling, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-10-08 19:22 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr Hi Sekhar, On 10/6/2010 11:37 AM, Nori, Sekhar wrote: > Hi Mike, > > On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: >> >> Let me know if you want testing on the DMA portion of the patch (when your ready, of course). > > I just finished pushing the DMA related patches to the git branch[1]. > I have not tested yet, but feel free to give it a go (maybe I will get > lucky again!). > I gave it a go for our platform. The good news is, polled and interrupt driven mode still work! The bad news is that DMA mode hangs up the kernel on the first read attempt, stalled waiting for the transfer completion notification (hmmm.... I think this was a spot where things were tweaked a bit? :) ) I'll see if I can narrow it down some more if you don't get to it first. > Also, do you have patches adding SPI support for DA850 platform? > I can include these patches on this branch so others who will be > testing don’t have to repeat the work. > I cloned your repository at [1] and published the additions needed to made to test it on the mitydsp-l138 platform (da850 based) at [2] (never mind the UART one at the end). I had to add clock support for the spi devices and define the platform SPI resources/registration routines. I'd appreciate a quick peek at those to make sure that I didn't make any errors. The spi registration may be refactorable (sp?) to support da830, I didn't look to closely at that. If any of it is usable, great. > Thanks, > Sekhar > > [1] http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite > [2] http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=shortlog;h=refs/heads/spi-testing -Mike _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source ^ permalink raw reply [flat|nested] 33+ messages in thread
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* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4CAF6F86.40201-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-10-09 12:55 ` Michael Williamson [not found] ` <4CB0665A.3000309-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-10-09 12:55 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr On 10/08/2010 03:22 PM, Michael Williamson wrote: > Hi Sekhar, > > On 10/6/2010 11:37 AM, Nori, Sekhar wrote: > >> Hi Mike, >> >> On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: >>> >>> Let me know if you want testing on the DMA portion of the patch (when your ready, of course). >> >> I just finished pushing the DMA related patches to the git branch[1]. >> I have not tested yet, but feel free to give it a go (maybe I will get >> lucky again!). >> > > > I gave it a go for our platform. The good news is, polled and interrupt driven mode still work! > The bad news is that DMA mode hangs up the kernel on the first read attempt, stalled waiting > for the transfer completion notification (hmmm.... I think this was a spot where things were > tweaked a bit? :) ) > > I'll see if I can narrow it down some more if you don't get to it first. > I think I found it. This patch (below, and on [2]) got it working for me. The Rx DMA size on transfer requests with no receive buffer provided needs to match the requested size (and the transmit size), not the size of the temporary buffer. All good as the DMA address increment is 0 in this case. I'll try to do some more testing next week, but so far so good. --- diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 662ebbe..8206df1 100755 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -632,13 +632,11 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) * source address never increments. */ - if (t->rx_buf) { + rx_buf_count = davinci_spi->rcount; + if (t->rx_buf) rx_buf = t->rx_buf; - rx_buf_count = davinci_spi->rcount; - } else { + else rx_buf = davinci_spi->rx_tmp_buf; - rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); - } t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, DMA_FROM_DEVICE); > >> Also, do you have patches adding SPI support for DA850 platform? >> I can include these patches on this branch so others who will be >> testing don\x19t have to repeat the work. >> > > > I cloned your repository at [1] and published the additions needed to made to test it on the > mitydsp-l138 platform (da850 based) at [2] (never mind the UART one at the end). I had to add > clock support for the spi devices and define the platform SPI resources/registration routines. > I'd appreciate a quick peek at those to make sure that I didn't make any errors. The spi > registration may be refactorable (sp?) to support da830, I didn't look to closely at that. > > If any of it is usable, great. > >> Thanks, >> Sekhar >> >> [1] http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite >> > > > [2] http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=shortlog;h=refs/heads/spi-testing > > -Mike ^ permalink raw reply related [flat|nested] 33+ messages in thread
[parent not found: <4CB0665A.3000309-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>]
* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4CB0665A.3000309-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-10-11 16:57 ` Nori, Sekhar [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302343630D8-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 33+ messages in thread From: Nori, Sekhar @ 2010-10-11 16:57 UTC (permalink / raw) To: Michael Williamson Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr Hi Mike, On Sat, Oct 09, 2010 at 18:25:54, Michael Williamson wrote: > On 10/08/2010 03:22 PM, Michael Williamson wrote: > > On 10/6/2010 11:37 AM, Nori, Sekhar wrote: > >> On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: > >> > >> I just finished pushing the DMA related patches to the git branch[1]. > >> I have not tested yet, but feel free to give it a go (maybe I will get > >> lucky again!). > >> > > > > > > I gave it a go for our platform. The good news is, polled and interrupt driven mode still work! > > The bad news is that DMA mode hangs up the kernel on the first read attempt, stalled waiting > > for the transfer completion notification (hmmm.... I think this was a spot where things were > > tweaked a bit? :) ) > > > > I'll see if I can narrow it down some more if you don't get to it first. > > > > I think I found it. This patch (below, and on [2]) got it working for me. The Rx DMA > size on transfer requests with no receive buffer provided needs to match the requested > size (and the transmit size), not the size of the temporary buffer. All good as the > DMA address increment is 0 in this case. > > I'll try to do some more testing next week, but so far so good. Sorry, I couldn’t get to testing even today. Should be on it tomorrow. > > --- > diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c > index 662ebbe..8206df1 100755 > --- a/drivers/spi/davinci_spi.c > +++ b/drivers/spi/davinci_spi.c > @@ -632,13 +632,11 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) > * source address never increments. > */ > > - if (t->rx_buf) { > + rx_buf_count = davinci_spi->rcount; > + if (t->rx_buf) > rx_buf = t->rx_buf; > - rx_buf_count = davinci_spi->rcount; > - } else { > + else > rx_buf = davinci_spi->rx_tmp_buf; > - rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); > - } > > t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, > DMA_FROM_DEVICE); Hmm, looks like the Tx and Rx DMA must always run for the same duration. I was under the impression Tx is required to keep the clock running, and so must always run for the length of transfer requested, but Rx DMA can finish earlier. I guess replacing the line: param.a_b_cnt = rx_buf_count << 16 | data_type; with param.a_b_cnt = davinci_spi->rcount << 16 | data_type; will also fix the issue? > > > > >> Also, do you have patches adding SPI support for DA850 platform? > >> I can include these patches on this branch so others who will be > >> testing don\x19t have to repeat the work. > >> > > > > > > I cloned your repository at [1] and published the additions needed to made to test it on the > > mitydsp-l138 platform (da850 based) at [2] (never mind the UART one at the end). I had to add > > clock support for the spi devices and define the platform SPI resources/registration routines. > > I'd appreciate a quick peek at those to make sure that I didn't make any errors. The spi > > registration may be refactorable (sp?) to support da830, I didn't look to closely at that. > > > > If any of it is usable, great. Sure it is! I checked-in your patches with some modifications to my branch. The most notable change being usage of da8xx instead of da850 since the same code should work on da830 as well. Apart from this there are some cosmetic changes (patches squashed, some non-relevant hunks dropped etc). Do update the patches in your tree if you are OK with the changes. Thanks, Sekhar _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <B85A65D85D7EB246BE421B3FB0FBB59302343630D8-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>]
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302343630D8-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> @ 2010-10-11 18:09 ` Michael Williamson [not found] ` <4CB352DF.70104-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> 2010-10-12 0:31 ` Michael Williamson 1 sibling, 1 reply; 33+ messages in thread From: Michael Williamson @ 2010-10-11 18:09 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr On 10/11/2010 12:57 PM, Nori, Sekhar wrote: > Hi Mike, > > On Sat, Oct 09, 2010 at 18:25:54, Michael Williamson wrote: >> On 10/08/2010 03:22 PM, Michael Williamson wrote: > >>> On 10/6/2010 11:37 AM, Nori, Sekhar wrote: > >>>> On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: > >>>> >>>> I just finished pushing the DMA related patches to the git branch[1]. >>>> I have not tested yet, but feel free to give it a go (maybe I will get >>>> lucky again!). >>>> >>> >>> >>> I gave it a go for our platform. The good news is, polled and interrupt driven mode still work! >>> The bad news is that DMA mode hangs up the kernel on the first read attempt, stalled waiting >>> for the transfer completion notification (hmmm.... I think this was a spot where things were >>> tweaked a bit? :) ) >>> >>> I'll see if I can narrow it down some more if you don't get to it first. >>> >> >> I think I found it. This patch (below, and on [2]) got it working for me. The Rx DMA >> size on transfer requests with no receive buffer provided needs to match the requested >> size (and the transmit size), not the size of the temporary buffer. All good as the >> DMA address increment is 0 in this case. >> >> I'll try to do some more testing next week, but so far so good. > > Sorry, I couldn’t get to testing even today. Should be on it > tomorrow. > >> >> --- >> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c >> index 662ebbe..8206df1 100755 >> --- a/drivers/spi/davinci_spi.c >> +++ b/drivers/spi/davinci_spi.c >> @@ -632,13 +632,11 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) >> * source address never increments. >> */ >> >> - if (t->rx_buf) { >> + rx_buf_count = davinci_spi->rcount; >> + if (t->rx_buf) >> rx_buf = t->rx_buf; >> - rx_buf_count = davinci_spi->rcount; >> - } else { >> + else >> rx_buf = davinci_spi->rx_tmp_buf; >> - rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); >> - } >> >> t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, >> DMA_FROM_DEVICE); > > Hmm, looks like the Tx and Rx DMA must always run for the same duration. I was > under the impression Tx is required to keep the clock running, and so must always > run for the length of transfer requested, but Rx DMA can finish earlier. > That may be true. The scenario I was seeing was a requested Tx length of 1 with no Rx buffer supplied. The length of the internal buffer was bigger than 1, so the resulting Rx DMA size in the a_b_cnt was greater than the Tx size, and it stalled. > I guess replacing the line: > > param.a_b_cnt = rx_buf_count << 16 | data_type; > > with > > param.a_b_cnt = davinci_spi->rcount << 16 | data_type; > > will also fix the issue? > A better fix. should be fine. >> >>> >>>> Also, do you have patches adding SPI support for DA850 platform? >>>> I can include these patches on this branch so others who will be >>>> testing don\x19t have to repeat the work. >>>> >>> >>> >>> I cloned your repository at [1] and published the additions needed to made to test it on the >>> mitydsp-l138 platform (da850 based) at [2] (never mind the UART one at the end). I had to add >>> clock support for the spi devices and define the platform SPI resources/registration routines. >>> I'd appreciate a quick peek at those to make sure that I didn't make any errors. The spi >>> registration may be refactorable (sp?) to support da830, I didn't look to closely at that. >>> >>> If any of it is usable, great. > > Sure it is! I checked-in your patches with some modifications to my > branch. The most notable change being usage of da8xx instead of da850 since > the same code should work on da830 as well. Apart from this there are > some cosmetic changes (patches squashed, some non-relevant hunks dropped > etc). Do update the patches in your tree if you are OK with the changes. > OK. I'll try to rebase off your tree and retest. -Mike _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source ^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <4CB352DF.70104-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>]
* RE: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <4CB352DF.70104-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org> @ 2010-10-12 12:14 ` Nori, Sekhar 0 siblings, 0 replies; 33+ messages in thread From: Nori, Sekhar @ 2010-10-12 12:14 UTC (permalink / raw) To: Michael Williamson Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr Hi Mike, On Mon, Oct 11, 2010 at 23:39:35, Michael Williamson wrote: > > > > Hmm, looks like the Tx and Rx DMA must always run for the same duration. I was > > under the impression Tx is required to keep the clock running, and so must always > > run for the length of transfer requested, but Rx DMA can finish earlier. > > > > That may be true. The scenario I was seeing was a requested Tx length of 1 with no > Rx buffer supplied. The length of the internal buffer was bigger than 1, so the resulting > Rx DMA size in the a_b_cnt was greater than the Tx size, and it stalled. > > > I guess replacing the line: > > > > param.a_b_cnt = rx_buf_count << 16 | data_type; > > > > with > > > > param.a_b_cnt = davinci_spi->rcount << 16 | data_type; > > > > will also fix the issue? > > > > A better fix. should be fine. I tested this on DA830 and DA850 EVMs with SPI nor flash - it works fine. I added your Tested-By to the DMA patches as well. Thanks for the testing and bug fixing. Updated set of patches pushed to my branch[1]. Testing on DM* platforms is the next task. Thanks, Sekhar [1] http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/davinci-spi-rewrite ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302343630D8-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2010-10-11 18:09 ` Michael Williamson @ 2010-10-12 0:31 ` Michael Williamson 1 sibling, 0 replies; 33+ messages in thread From: Michael Williamson @ 2010-10-12 0:31 UTC (permalink / raw) To: Nori, Sekhar Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org, Brian Niebuhr On 10/11/2010 12:57 PM, Nori, Sekhar wrote: > Hi Mike, > > On Sat, Oct 09, 2010 at 18:25:54, Michael Williamson wrote: >> On 10/08/2010 03:22 PM, Michael Williamson wrote: > >>> On 10/6/2010 11:37 AM, Nori, Sekhar wrote: > >>>> On Mon, Sep 20, 2010 at 23:12:53, Michael Williamson wrote: > >>>> >>>> I just finished pushing the DMA related patches to the git branch[1]. [ stuff deleted ] >> >>> >>>> Also, do you have patches adding SPI support for DA850 platform? >>>> I can include these patches on this branch so others who will be >>>> testing don\x19t have to repeat the work. >>>> >>> >>> >>> I cloned your repository at [1] and published the additions needed to made to test it on the >>> mitydsp-l138 platform (da850 based) at [2] (never mind the UART one at the end). I had to add >>> clock support for the spi devices and define the platform SPI resources/registration routines. >>> I'd appreciate a quick peek at those to make sure that I didn't make any errors. The spi >>> registration may be refactorable (sp?) to support da830, I didn't look to closely at that. >>> >>> If any of it is usable, great. > > Sure it is! I checked-in your patches with some modifications to my > branch. The most notable change being usage of da8xx instead of da850 since > the same code should work on da830 as well. Apart from this there are > some cosmetic changes (patches squashed, some non-relevant hunks dropped > etc). Do update the patches in your tree if you are OK with the changes. > I think that the spi device names in the clk_lookup table in da830.c may need to be updated. Right now they are shown as "dm_spi.0". Should they be "spi_davinci.o" and "spi_davinci.1"? -Mike ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2010-08-02 15:53 ` Nori, Sekhar @ 2010-08-03 7:33 ` Grant Likely 2010-08-03 7:55 ` Christophe Aeschlimann 2 siblings, 0 replies; 33+ messages in thread From: Grant Likely @ 2010-08-03 7:33 UTC (permalink / raw) To: Brian Niebuhr Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ On Mon, Aug 2, 2010 at 8:10 AM, Brian Niebuhr <bniebuhr3-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > Grant - > > That's fine - I understand your position. I do wish you had decided > earlier that you weren't going to accept the patch in that form though > so I could have decided whether I wanted to spend any more time on it. > For my part, I've already sunk way more time into this than I ever > intended, and I really have no clue how to break this patch down into > smaller patches. I don't really care much if the patch gets accepted > or not - I am just trying to help out all of the other users that are > stuck with a broken driver like I was. Hi Brian. I'm sorry to hear that, but I totally understand having heavy demands on your time. Thanks for the work that you have done. I know it is frustrating when things don't go in as easily as hoped. I also want to see your changes merged, but I also have to be mindful of other engineers looking at your commit after the fact and being able to bisect it. If you do change your mind, my offer still stands to help you break the patch down into logical pieces. It is actually pretty easy to do. > Maybe if TI wants to give > their customers a driver that actually works they'll pick it up and do > the rest of the work that's necessary to get it accepted. I'm just > way too swamped with other work to keep going on this. > > Thanks for your help though. Sorry to waste all of the time you've > put into this. It hasn't been wasted time. You've done all the hard work. Sounds like Sekhar from TI will pick up the driver and split it up, which is an almost mechanical process when you know how to do it. Thanks for the time you have spent on this. Cheers, g. ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 1/1] davinci: spi: replace existing driver [not found] ` <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2010-08-02 15:53 ` Nori, Sekhar 2010-08-03 7:33 ` Grant Likely @ 2010-08-03 7:55 ` Christophe Aeschlimann 2 siblings, 0 replies; 33+ messages in thread From: Christophe Aeschlimann @ 2010-08-03 7:55 UTC (permalink / raw) To: Brian Niebuhr Cc: Grant Likely, spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/ Hi, On 02.08.2010 16:10, Brian Niebuhr wrote: > Grant - [...] > I am just trying to help out all of the other users that are > stuck with a broken driver like I was. Thank you Brian. The work you've done there is very much appreciated. > Maybe if TI wants to give their customers a driver that actually > works they'll pick it up and do the rest of the work that's necessary > to get it accepted. It seems they got the message ! :) > Brian Regards, -- Christophe Aeschlimann Embedded Software Engineer Advanced Communications Networks S.A. Rue du Puits-Godet 8a 2000 Neuchâtel, Switzerland Tél. +41 32 724 74 31 c.aeschlimann-5/WUhD8XThOVQ4qyx6sgCw@public.gmane.org ^ permalink raw reply [flat|nested] 33+ messages in thread
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Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
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2010-07-28 22:18 [PATCH v5 0/1] davinci: spi: replace existing driver Brian Niebuhr
[not found] ` <1280355490-11878-1-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org>
2010-07-28 22:18 ` [PATCH v5 1/1] " Brian Niebuhr
[not found] ` <1280355490-11878-2-git-send-email-bniebuhr-JaPwekKOx1yaMJb+Lgu22Q@public.gmane.org>
2010-08-01 5:12 ` Grant Likely
[not found] ` <AANLkTimu+G-5wTrdQ6YiWi60i+5uN9sydfsZKMKQX7_f-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-08-02 14:10 ` Brian Niebuhr
[not found] ` <AANLkTim-FB6YrGSTmDQhmnS+Qw-dGm7D-pH7iCzy0-Td-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-08-02 15:53 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E7ED0A13-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-08-20 11:06 ` Caglar Akyuz
[not found] ` <201008201406.33473.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2010-08-20 14:46 ` Todd Fischer
2010-08-20 17:19 ` Grant Likely
2010-08-23 4:28 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350B45-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-08-23 4:40 ` Grant Likely
2010-08-23 8:54 ` Caglar Akyuz
[not found] ` <201008231154.10411.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2010-08-23 9:30 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301E8350E47-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-09-13 23:45 ` Michael Williamson
[not found] ` <4C8EB795.1080607-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-09-14 5:43 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4C95-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-09-14 6:04 ` Caglar Akyuz
[not found] ` <201009140904.59555.caglarakyuz-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2010-09-14 7:14 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF4D9B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-09-14 13:10 ` Michael Williamson
[not found] ` <4C8F7460.6050006-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-09-14 13:26 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6DF50C1-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-09-18 13:08 ` Michael Williamson
[not found] ` <4C94B9BD.4010606-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-09-18 13:16 ` Michael Williamson
2010-09-20 15:08 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59301F6F5385B-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-09-20 17:42 ` Michael Williamson
[not found] ` <4C979D1D.1070707-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-09-27 17:35 ` Nori, Sekhar
2010-10-06 15:37 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302342050C7-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-10-07 3:55 ` Michael Williamson
2010-10-08 19:22 ` Michael Williamson
[not found] ` <4CAF6F86.40201-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-10-09 12:55 ` Michael Williamson
[not found] ` <4CB0665A.3000309-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-10-11 16:57 ` Nori, Sekhar
[not found] ` <B85A65D85D7EB246BE421B3FB0FBB59302343630D8-/tLxBxkBPtCIQmiDNMet8wC/G2K4zDHf@public.gmane.org>
2010-10-11 18:09 ` Michael Williamson
[not found] ` <4CB352DF.70104-wZX4cNJlHJ2sVWG7oymsAA@public.gmane.org>
2010-10-12 12:14 ` Nori, Sekhar
2010-10-12 0:31 ` Michael Williamson
2010-08-03 7:33 ` Grant Likely
2010-08-03 7:55 ` Christophe Aeschlimann
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