Issue linked to component 821034 from IDT

Issue linked to component 821034 from IDT

[LEROY christophe]

Good afternoon,

I'm trying to program a Quad CODEC from IDT reference 821034 through 
SPI, and I'm having an issue:

The component requires 2 clock cycles in addition after setting CS back 
to inactive state, otherwise the transmitted data is not latched in. I'm 
wondering how I could do that easily in a Linux driver using the 
standard SPI subsystem.
What I could do is to transmit a 2 bits data after setting CS to OFF 
state, but how can I do that ?

Also, another issue I have is that between each byte I shall set CS to 
OFF for at least 3 clock cycles. This can be done of course by sending 
bytes one by one, but is there another easy way to do the same by 
configuration ?

Regards
C. Leroy

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