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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89c440d4594sm48468046d6.5.2026.03.16.10.13.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 10:13:28 -0700 (PDT) Subject: Re: [PATCH v1] spi: geni-qcom: Fix CPHA and CPOL mode change detection To: Maramaina Naresh , Mark Brown , konrad.dybcio@oss.qualcomm.com Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, bjorande@quicinc.com, mukesh.savaliya@oss.qualcomm.com, praveen.talari@oss.qualcomm.com, jyothi.seerapu@oss.qualcomm.com References: <20260316-spi-geni-cpha-cpol-fix-v1-1-4cb44c176b79@oss.qualcomm.com> From: Jonathan Marek Message-ID: <4a7d89ef-0f63-a7c3-e996-ff9fc476a04e@marek.ca> Date: Mon, 16 Mar 2026 13:13:07 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260316-spi-geni-cpha-cpol-fix-v1-1-4cb44c176b79@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Reviewed-by: Jonathan Marek at least it doesn't look like this stupid mistake breaks anything upstream (no spi-cpha/spi-cpol in any qcom dts) On 3/16/26 9:23 AM, Maramaina Naresh wrote: > setup_fifo_params computes mode_changed from spi->mode flags but tests > it against SE_SPI_CPHA and SE_SPI_CPOL, which are register offsets, > not SPI mode bits. This causes CPHA and CPOL updates to be skipped > on mode switches, leaving the controller with stale clock phase > and polarity settings. > > Fix this by using SPI_CPHA and SPI_CPOL to detect mode changes before > updating the corresponding registers. > > Fixes: 781c3e71c94c ("spi: spi-geni-qcom: rework setup_fifo_params") > Signed-off-by: Maramaina Naresh > --- > This patch fixes SPI mode change detection in the spi-geni-qcom driver. > > setup_fifo_params compared spi->mode against SE_SPI_CPHA/SE_SPI_CPOL, > which are register offsets instead of SPI_CPHA/SPI_CPOL mode bits. > This could skip CPHA/CPOL updates on mode switches and leave stale > clock configuration. > > This is a single-patch series. > --- > drivers/spi/spi-geni-qcom.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index 43ce47f2454c..772b7148ba5f 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -359,9 +359,9 @@ static int setup_fifo_params(struct spi_device *spi_slv, > writel((spi_slv->mode & SPI_LOOP) ? LOOPBACK_ENABLE : 0, se->base + SE_SPI_LOOPBACK); > if (cs_changed) > writel(chipselect, se->base + SE_SPI_DEMUX_SEL); > - if (mode_changed & SE_SPI_CPHA) > + if (mode_changed & SPI_CPHA) > writel((spi_slv->mode & SPI_CPHA) ? CPHA : 0, se->base + SE_SPI_CPHA); > - if (mode_changed & SE_SPI_CPOL) > + if (mode_changed & SPI_CPOL) > writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL); > if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH))) > writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV); > > --- > base-commit: 7109a2155340cc7b21f27e832ece6df03592f2e8 > change-id: 20260316-spi-geni-cpha-cpol-fix-89126ed55325 > > Best regards, >