[PATCH 00/17] Add memory mapped support for ti qspi, m25p80 serial flash.

[PATCH 00/17] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

The patch series aims to add memory mapped support for TI qspi
contoller and also add support for the same in serial flash driver(m25p80).

These feature was added as a part of the series[1]:
The series[1] add support for quad and memory mapped feature in spi and
flash driver. Based on Brian Norris suggestion on splitting the quad and 
memory mapped feature, I had sent a seperate series for quad support which 
has beed accepted by Brian.

The $subject patch series takes care of the memory mapped part.  

Overview of memory mapped support in qspi:
 TI qspi controller supports memory mapped read support, switching to which
 requires  register modifications(qspi registers, control module register for
 DRA, qspi register for am43x). Once switched, the flash data can be available
 at a soc specific memory mapped address. For operations in normal mode, we need 
 to keep memory mapped disable.

 Flow of the patch is to keep the memory mapped enable by default in the driver.
 Whenever Normal spi mode operations are desired, we switch to configuration mode
 and at the end of it memory mapped is again enabled. There are few function pointers
 added to fecilitate easy communication between the flash and spi controllers.

Major changes in the $subject patch based on discussion in [1]:

- Feature has been broken down into small meaningfl patches.
- memcpy is done in flash driver and spi framework is bypassed.
- configuration of memory mapped spi controller regsiters is done
  through function calls from flash side.

[1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html


Tested on DRA7 board with spansion S25FL256S flash along with some
internal irq crossbar patches.
Tested on AM437x epos evm with macronix MX66l51235l flash.

Testing done:
-Erase the whole flash.
-write to the flash
-read back the flash
- compare the data

Sourav Poddar (17):
  spi/spi.h: Add get_buf/put_buf support in spi master..
  spi/spi.h: Add configure from slave support.
  spi/qspi: parse register by name.
  spi/qspi: parse control module register.
  spi/qspi: parse memory map register.
  spi/qspi: Add support to switc to memory mapped operation.
  spi/qspi: configure set up register for memory map..
  spi/qspi: Add api for get_buf/put_buf.
  spi/spi.h: Add "mem" variable in spi master.
  spi/spi.h: Add mmap flag in spi master.
  spi/qspi: set "mmap" flag to true.
  spi/qspi: convert driver to enable/disable memory mapped..
  drivers: mtd: m25p80: Add api to configure master register .
  drivers: mtd: m25p80: Adapt driver to support memory mapped read.
  arm: dts: dra7: Add qspi device.
  arm: dts: am43x-epos: Add qspi device.
  Documentation: bindings: ti-qspi: update binding information.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    2 +
 arch/arm/boot/dts/am4372.dtsi                     |   12 ++
 arch/arm/boot/dts/am43x-epos-evm.dts              |   28 +++++
 arch/arm/boot/dts/dra7-evm.dts                    |   32 ++++++
 arch/arm/boot/dts/dra7.dtsi                       |   13 +++
 drivers/mtd/devices/m25p80.c                      |   30 ++++++
 drivers/spi/spi-ti-qspi.c                         |  115 ++++++++++++++++++++-
 include/linux/spi/spi.h                           |   16 +++
 8 files changed, 246 insertions(+), 2 deletions(-)

[PATCH 03/17] spi/qspi: parse register by name.

[Sourav Poddar]

Modify the qspi driver to parse reg information by name.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..67aa905 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -465,7 +465,11 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	qspi->master = master;
 	qspi->dev = &pdev->dev;
 
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
+	if (r == NULL) {
+		dev_err(&pdev->dev, "missing platform resources data\n");
+		return -ENODEV;
+	}
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
-- 
1.7.1

Re: [PATCH 03/17] spi/qspi: parse register by name.

[Mark Brown]

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On Tue, Nov 26, 2013 at 01:04:59PM +0530, Sourav Poddar wrote:
> Modify the qspi driver to parse reg information by name.

This presumably needs an update to the device tree bindings so that
there's a name defined?

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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Sourav Poddar]

On Tuesday 26 November 2013 04:00 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:04:59PM +0530, Sourav Poddar wrote:
>> Modify the qspi driver to parse reg information by name.
> This presumably needs an update to the device tree bindings so that
> there's a name defined?
I have added "reg-names" property in dt bindings. (17/17) patch of
this series has that info.
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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Mark Brown]

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On Tue, Nov 26, 2013 at 04:47:49PM +0530, Sourav Poddar wrote:

> I have added "reg-names" property in dt bindings. (17/17) patch of
> this series has that info.

Do device tree binding changes early on in the series rather than at the
end, one of the things that gets reviewed for is binding updates.

Your code should also cope with the existing bindings, falling back on
the current behaviour if it can't get the names or the extra resources.

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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Sourav Poddar]

On Tuesday 26 November 2013 05:54 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 04:47:49PM +0530, Sourav Poddar wrote:
>
>> I have added "reg-names" property in dt bindings. (17/17) patch of
>> this series has that info.
> Do device tree binding changes early on in the series rather than at the
> end, one of the things that gets reviewed for is binding updates.
>
> Your code should also cope with the existing bindings, falling back on
> the current behaviour if it can't get the names or the extra resources.
My current code only has a single resouce, hence "*_byname* variants
was not used. With extra resources, I am switching to "byname" variants,
So, if a particular resource name is not found, it should just bypass 
that, thinking
the resource is not required and should not resort to existing bindings..

Re: [PATCH 03/17] spi/qspi: parse register by name.

[Mark Brown]

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On Thu, Nov 28, 2013 at 10:15:14AM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 05:54 PM, Mark Brown wrote:

> >Do device tree binding changes early on in the series rather than at the
> >end, one of the things that gets reviewed for is binding updates.

> >Your code should also cope with the existing bindings, falling back on
> >the current behaviour if it can't get the names or the extra resources.

> My current code only has a single resouce, hence "*_byname* variants
> was not used. With extra resources, I am switching to "byname" variants,
> So, if a particular resource name is not found, it should just
> bypass that, thinking
> the resource is not required and should not resort to existing bindings..

That means that if you switch all resources to _byname then the driver
won't find any resources at all and will fail.  This will in turn mean
that any device trees that work with the current code wil start failing,
breaking compatibility.

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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Sourav Poddar]

On Thursday 28 November 2013 04:24 PM, Mark Brown wrote:
> On Thu, Nov 28, 2013 at 10:15:14AM +0530, Sourav Poddar wrote:
>> On Tuesday 26 November 2013 05:54 PM, Mark Brown wrote:
>>> Do device tree binding changes early on in the series rather than at the
>>> end, one of the things that gets reviewed for is binding updates.
>>> Your code should also cope with the existing bindings, falling back on
>>> the current behaviour if it can't get the names or the extra resources.
>> My current code only has a single resouce, hence "*_byname* variants
>> was not used. With extra resources, I am switching to "byname" variants,
>> So, if a particular resource name is not found, it should just
>> bypass that, thinking
>> the resource is not required and should not resort to existing bindings..
> That means that if you switch all resources to _byname then the driver
> won't find any resources at all and will fail.  This will in turn mean
> that any device trees that work with the current code wil start failing,
> breaking compatibility.
I am changing my code to use *byname for all resources. There is no
dts available now in mainline using this code. I have added the dts file
as patch 15, 16 of this series to take care of this.
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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Mark Brown]

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On Thu, Nov 28, 2013 at 04:28:07PM +0530, Sourav Poddar wrote:
> On Thursday 28 November 2013 04:24 PM, Mark Brown wrote:

> >That means that if you switch all resources to _byname then the driver
> >won't find any resources at all and will fail.  This will in turn mean
> >that any device trees that work with the current code wil start failing,
> >breaking compatibility.

> I am changing my code to use *byname for all resources. There is no
> dts available now in mainline using this code. I have added the dts file
> as patch 15, 16 of this series to take care of this.

We're now aiming for DT to be a stable interface and the existing
binding has been included in a release so you really ought to be keeping
compatiblity.

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Re: [PATCH 03/17] spi/qspi: parse register by name.

[Sourav Poddar]

On Thursday 28 November 2013 04:41 PM, Mark Brown wrote:
> On Thu, Nov 28, 2013 at 04:28:07PM +0530, Sourav Poddar wrote:
>> On Thursday 28 November 2013 04:24 PM, Mark Brown wrote:
>>> That means that if you switch all resources to _byname then the driver
>>> won't find any resources at all and will fail.  This will in turn mean
>>> that any device trees that work with the current code wil start failing,
>>> breaking compatibility.
>> I am changing my code to use *byname for all resources. There is no
>> dts available now in mainline using this code. I have added the dts file
>> as patch 15, 16 of this series to take care of this.
> We're now aiming for DT to be a stable interface and the existing
> binding has been included in a release so you really ought to be keeping
> compatiblity.
Ok. So I will check for *byname, if not found I will switch to 
"platform_get_resource".
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[PATCH 07/17] spi/qspi: configure set up register for memory map..

[Sourav Poddar]

These add api to configure set up registers which will be used
for memory mapped operations.

These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 40f1c35..2323572 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
 #define MEM_CS		(1 << 8)
 #define MEM_CS_DIS	(0 << 8)
 
+#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
+#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
+#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -220,6 +224,29 @@ static int ti_qspi_setup(struct spi_device *spi)
 	return 0;
 }
 
+static void ti_qspi_configure_from_slave(struct spi_device *spi, u8 *val)
+{
+	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
+	u32 memval, mode;
+
+	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
+	memval =  (val[0] << 0) | (val[1] << 16) |
+			((val[2] - 1) << 8) | (val[3] << 10);
+
+	switch (mode) {
+	case SPI_RX_DUAL:
+		memval |= QSPI_SETUP0_RD_DUAL;
+		break;
+	case SPI_RX_QUAD:
+		memval |= QSPI_SETUP0_RD_QUAD;
+		break;
+	default:
+		memval |= QSPI_SETUP0_RD_NORMAL;
+		break;
+	}
+	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -487,6 +514,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->transfer_one_message = ti_qspi_start_transfer_one;
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+	master->configure_from_slave = ti_qspi_configure_from_slave;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCH 01/17] spi/spi.h: Add get_buf/put_buf support in spi master..

[Sourav Poddar]

Add get_buf, put_buf api support in spi master.
This can be used in a scenario where spi controller
supports memory mapped operations(typically with flash devices).
So, the memcpy needs top be done in slave devices which need the
required memory mapped address. These api can be used to get that
master address.

These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 include/linux/spi/spi.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba7..3b3743d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -291,6 +291,10 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *	number. Any individual value may be -ENOENT for CS lines that
  *	are not GPIOs (driven by the SPI controller itself).
  *
+ * @get_buf: used for memory mapped cases, when the slave device wants to
+ *       know the address to be used for memcopy.
+ * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
+ *       has finished.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -421,6 +425,9 @@ struct spi_master {
 	int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
 			    struct spi_transfer *transfer);
 
+	void	(*get_buf)(struct spi_master *master);
+	void	(*put_buf)(struct spi_master *master);
+
 	/* gpio chip select */
 	int			*cs_gpios;
 };
-- 
1.7.1

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Re: [PATCH 01/17] spi/spi.h: Add get_buf/put_buf support in spi master..

[Mark Brown]

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On Tue, Nov 26, 2013 at 01:04:57PM +0530, Sourav Poddar wrote:

> Add get_buf, put_buf api support in spi master.
> This can be used in a scenario where spi controller

I would expect that while the buffer is mapped the controller would be
unavailable for normal SPI API use so I'd expect some code that checks a
flag while a mapping is in place and errors out on normal SPI operations
during that time as well as the operations themselves.

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[PATCH 02/17] spi/spi.h: Add configure from slave support.

[Sourav Poddar]

There are few use cases encountered where the master controller
depends on the slave parameters for some of its register
configure. Add an api in spi master which can be used to enable the
above feature.

Typical usecase encountered till now is
- ti qspi controller required flash opcodes to configure its set up
   register for memory mapped operations.

There was another discussion on some LUT registers for some other
qspi controller in mailing list, these feature can also be used for
that case also.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 include/linux/spi/spi.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 3b3743d..4be969a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -295,6 +295,9 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *       know the address to be used for memcopy.
  * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
  *       has finished.
+ * @configure_from_slave: Used when SPI controller has registers which need
+ *      to be configured from slave specifics information(typical use case for
+ *      SPI flash device).
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -427,6 +430,7 @@ struct spi_master {
 
 	void	(*get_buf)(struct spi_master *master);
 	void	(*put_buf)(struct spi_master *master);
+	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);
 
 	/* gpio chip select */
 	int			*cs_gpios;
-- 
1.7.1

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Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.

[Mark Brown]

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On Tue, Nov 26, 2013 at 01:04:58PM +0530, Sourav Poddar wrote:

>  	void	(*get_buf)(struct spi_master *master);
>  	void	(*put_buf)(struct spi_master *master);
> +	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);

Clearly this is far too unstructured to be useful, this is only ever
going to work with one specific combination of slave and master since
there's absolutely no semantics defined.

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Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.

[Sourav Poddar]

On Tuesday 26 November 2013 03:59 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:04:58PM +0530, Sourav Poddar wrote:
>
>>   	void	(*get_buf)(struct spi_master *master);
>>   	void	(*put_buf)(struct spi_master *master);
>> +	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);
> Clearly this is far too unstructured to be useful, this is only ever
> going to work with one specific combination of slave and master since
> there's absolutely no semantics defined.
I thought "val" might be good enuf, and this can be filled with whatever
data that need to be used from slave into master(irrespective of slave 
and master?).

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Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.

[Mark Brown]

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On Tue, Nov 26, 2013 at 04:51:53PM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 03:59 PM, Mark Brown wrote:

> >>+	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);

> >Clearly this is far too unstructured to be useful, this is only ever
> >going to work with one specific combination of slave and master since
> >there's absolutely no semantics defined.

> I thought "val" might be good enuf, and this can be filled with whatever
> data that need to be used from slave into master(irrespective of
> slave and master?).

The name isn't the issue, it's the fact that you're passing a completely
unspecified blob of data.

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Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.

[Sourav Poddar]

On Tuesday 26 November 2013 05:51 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 04:51:53PM +0530, Sourav Poddar wrote:
>> On Tuesday 26 November 2013 03:59 PM, Mark Brown wrote:
>>>> +	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);
>>> Clearly this is far too unstructured to be useful, this is only ever
>>> going to work with one specific combination of slave and master since
>>> there's absolutely no semantics defined.
>> I thought "val" might be good enuf, and this can be filled with whatever
>> data that need to be used from slave into master(irrespective of
>> slave and master?).
> The name isn't the issue, it's the fact that you're passing a completely
> unspecified blob of data.
May be, what you are suggesting here is to we should define a flash 
information
structure and should pass that structure here ?

Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.

[Mark Brown]

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On Thu, Nov 28, 2013 at 10:17:38AM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 05:51 PM, Mark Brown wrote:

> >The name isn't the issue, it's the fact that you're passing a completely
> >unspecified blob of data.

> May be, what you are suggesting here is to we should define a flash
> information
> structure and should pass that structure here ?

Possibly, that's definitely moving towards adding more structure.

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[PATCH 04/17] spi/qspi: parse control module register.

[Sourav Poddar]

In qspi controller, we need to switch to memory mapped operations.
These switching depends on

1. For DRA7x: qspi register bit and control module register.
2. For AM437x: qspi register bit.

Hence add support for parsing control module register and provide a
flag "ctrl_mod" which can be used for conditional execution of
control module part.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/spi/spi-ti-qspi.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 67aa905..776e93d 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,7 @@ struct ti_qspi {
 
 	struct spi_master	*master;
 	void __iomem            *base;
+	void __iomem            *ctrl_base;
 	struct clk		*fclk;
 	struct device           *dev;
 
@@ -54,6 +55,8 @@ struct ti_qspi {
 	u32 spi_max_frequency;
 	u32 cmd;
 	u32 dc;
+
+	bool ctrl_mod;
 };
 
 #define QSPI_PID			(0x0)
@@ -437,7 +440,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 {
 	struct  ti_qspi *qspi;
 	struct spi_master *master;
-	struct resource         *r;
+	struct resource         *r, *res_ctrl;
 	struct device_node *np = pdev->dev.of_node;
 	u32 max_freq;
 	int ret = 0, num_cs, irq;
@@ -471,6 +474,9 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	res_ctrl = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_ctrlmod");
+
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		dev_err(&pdev->dev, "no irq resource?\n");
@@ -485,6 +491,15 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		goto free_master;
 	}
 
+	if (res_ctrl) {
+		qspi->ctrl_mod = true;
+		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
+		if (IS_ERR(qspi->ctrl_base)) {
+			ret = PTR_ERR(qspi->ctrl_base);
+			goto free_master;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 			dev_name(&pdev->dev), qspi);
 	if (ret < 0) {
-- 
1.7.1

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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 208 bytes --]

On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote:
> In qspi controller, we need to switch to memory mapped operations.
> These switching depends on

This will need to be added to the DT binding.

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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Sourav Poddar]

On Tuesday 26 November 2013 04:01 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote:
>> In qspi controller, we need to switch to memory mapped operations.
>> These switching depends on
> This will need to be added to the DT binding.


I have added a "reg-name" property. Does we need to add individual 
reg-names also?


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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 488 bytes --]

On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 04:01 PM, Mark Brown wrote:
> >On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote:
> >>In qspi controller, we need to switch to memory mapped operations.
> >>These switching depends on

> >This will need to be added to the DT binding.

> I have added a "reg-name" property. Does we need to add individual
> reg-names also?

I don't understand what you mean by "individual reg-names"?

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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Sourav Poddar]

On Tuesday 26 November 2013 05:55 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote:
>> On Tuesday 26 November 2013 04:01 PM, Mark Brown wrote:
>>> On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote:
>>>> In qspi controller, we need to switch to memory mapped operations.
>>>> These switching depends on
>>> This will need to be added to the DT binding.
>> I have added a "reg-name" property. Does we need to add individual
>> reg-names also?
> I don't understand what you mean by "individual reg-names"?
I have added a binding named "reg-names" in my documentation
patch.
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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 460 bytes --]

On Tue, Nov 26, 2013 at 06:08:34PM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 05:55 PM, Mark Brown wrote:
> >On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote:

> >>I have added a "reg-name" property. Does we need to add individual
> >>reg-names also?

> >I don't understand what you mean by "individual reg-names"?

> I have added a binding named "reg-names" in my documentation
> patch.

OK, but I stil don't understand the above?

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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Sourav Poddar]

On Tuesday 26 November 2013 06:25 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 06:08:34PM +0530, Sourav Poddar wrote:
>> On Tuesday 26 November 2013 05:55 PM, Mark Brown wrote:
>>> On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote:
>>>> I have added a "reg-name" property. Does we need to add individual
>>>> reg-names also?
>>> I don't understand what you mean by "individual reg-names"?
>> I have added a binding named "reg-names" in my documentation
>> patch.
> OK, but I stil don't understand the above?
I mean to say, do I need to document "qspi_base", "qspi_ctrlmod" 
register names
also which I have used in omy dts files.


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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 263 bytes --]

On Tue, Nov 26, 2013 at 06:30:15PM +0530, Sourav Poddar wrote:

> I mean to say, do I need to document "qspi_base", "qspi_ctrlmod"
> register names
> also which I have used in omy dts files.

Yes, you need to document what the valid names are and what they mean.

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Re: [PATCH 04/17] spi/qspi: parse control module register.

[Sourav Poddar]

On Tuesday 26 November 2013 06:49 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 06:30:15PM +0530, Sourav Poddar wrote:
>
>> I mean to say, do I need to document "qspi_base", "qspi_ctrlmod"
>> register names
>> also which I have used in omy dts files.
> Yes, you need to document what the valid names are and what they mean.
Ok, will do that.


Thanks
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[PATCH 05/17] spi/qspi: parse memory map register.

[Sourav Poddar]

Parse memory map register from device tree.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/spi/spi-ti-qspi.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 776e93d..39aefd7 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -47,6 +47,7 @@ struct ti_qspi {
 	struct spi_master	*master;
 	void __iomem            *base;
 	void __iomem            *ctrl_base;
+	void __iomem            *mmap_base;
 	struct clk		*fclk;
 	struct device           *dev;
 
@@ -440,7 +441,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 {
 	struct  ti_qspi *qspi;
 	struct spi_master *master;
-	struct resource         *r, *res_ctrl;
+	struct resource         *r, *res_ctrl, *res_mmap;
 	struct device_node *np = pdev->dev.of_node;
 	u32 max_freq;
 	int ret = 0, num_cs, irq;
@@ -477,6 +478,9 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	res_ctrl = platform_get_resource_byname(pdev,
 			IORESOURCE_MEM, "qspi_ctrlmod");
 
+	res_mmap = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_mmap");
+
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
 		dev_err(&pdev->dev, "no irq resource?\n");
@@ -500,6 +504,14 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (res_mmap) {
+		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
+		if (IS_ERR(qspi->mmap_base)) {
+			ret = PTR_ERR(qspi->mmap_base);
+			goto free_master;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 			dev_name(&pdev->dev), qspi);
 	if (ret < 0) {
-- 
1.7.1

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[PATCH 06/17] spi/qspi: Add support to switc to memory mapped operation.

[Sourav Poddar]

These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/spi/spi-ti-qspi.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 39aefd7..40f1c35 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -113,6 +113,10 @@ struct ti_qspi {
 #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
 #define QSPI_CKPOL(n)			(1 << (n * 8))
 
+#define MM_SWITCH	(1 << 0)
+#define MEM_CS		(1 << 8)
+#define MEM_CS_DIS	(0 << 8)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
 	writel(val, qspi->base + reg);
 }
 
+void enable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val |= MEM_CS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
+void disable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val &= MEM_CS_DIS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
 static int ti_qspi_setup(struct spi_device *spi)
 {
 	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
-- 
1.7.1

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Re: [PATCH 06/17] spi/qspi: Add support to switc to memory mapped operation.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 341 bytes --]

On Tue, Nov 26, 2013 at 01:05:02PM +0530, Sourav Poddar wrote:

> +void enable_qspi_memory_mapped(struct ti_qspi *qspi)

> +void disable_qspi_memory_mapped(struct ti_qspi *qspi)

These are driver internal functions so they should be static.  It'd also
be more normal to put the qspi_ at the start of the name though it's not
too big a deal.

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Re: [PATCH 06/17] spi/qspi: Add support to switc to memory mapped operation.

[Sourav Poddar]

On Tuesday 26 November 2013 06:27 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:05:02PM +0530, Sourav Poddar wrote:
>
>> +void enable_qspi_memory_mapped(struct ti_qspi *qspi)
>> +void disable_qspi_memory_mapped(struct ti_qspi *qspi)
> These are driver internal functions so they should be static.  It'd also
> be more normal to put the qspi_ at the start of the name though it's not
> too big a deal.
Ok. will change.

[PATCH 08/17] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/spi/spi-ti-qspi.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 2323572..10bcb37 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -247,6 +247,21 @@ static void ti_qspi_configure_from_slave(struct spi_device *spi, u8 *val)
 	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
 }
 
+static void ti_qspi_get_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	pm_runtime_get_sync(qspi->dev);
+	master->mem = qspi->mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	pm_runtime_put(qspi->dev);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -515,6 +530,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->configure_from_slave = ti_qspi_configure_from_slave;
+	master->get_buf = ti_qspi_get_mem_buf;
+	master->put_buf = ti_qspi_put_mem_buf;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

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[PATCH 09/17] spi/spi.h: Add "mem" variable in spi master.

[Sourav Poddar]

Add "mem" variable in spi_master, which can be used to hold on the
memory mapped address.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 include/linux/spi/spi.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 4be969a..72565ff 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -298,6 +298,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  * @configure_from_slave: Used when SPI controller has registers which need
  *      to be configured from slave specifics information(typical use case for
  *      SPI flash device).
+ * @mem: memory mapped address to be filled by master controller driver.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -432,6 +433,8 @@ struct spi_master {
 	void	(*put_buf)(struct spi_master *master);
 	void	(*configure_from_slave)(struct spi_device *spi, u8 *val);
 
+	void __iomem *mem;
+
 	/* gpio chip select */
 	int			*cs_gpios;
 };
-- 
1.7.1

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Re: [PATCH 09/17] spi/spi.h: Add "mem" variable in spi master.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 232 bytes --]

On Tue, Nov 26, 2013 at 01:05:05PM +0530, Sourav Poddar wrote:
> Add "mem" variable in spi_master, which can be used to hold on the
> memory mapped address.

Is this really generic enough to put here rather than in the driver
data?

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Re: [PATCH 09/17] spi/spi.h: Add "mem" variable in spi master.

[Sourav Poddar]

On Tuesday 26 November 2013 06:31 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:05:05PM +0530, Sourav Poddar wrote:
>> Add "mem" variable in spi_master, which can be used to hold on the
>> memory mapped address.
> Is this really generic enough to put here rather than in the driver
> data?
The thought behind this was that if a master controller supports
memory mapped operation and slave wants to use memcpy in his
driver(bypassing spi ), then we should have a mean to communicate 
between the
master and the slave. So, 'spi_master' seems to be the place for me for 
this data,
which could be parsed in the slave side also.
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Re: [PATCH 09/17] spi/spi.h: Add "mem" variable in spi master.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 694 bytes --]

On Tue, Nov 26, 2013 at 06:35:35PM +0530, Sourav Poddar wrote:
> On Tuesday 26 November 2013 06:31 PM, Mark Brown wrote:

> >Is this really generic enough to put here rather than in the driver
> >data?

> The thought behind this was that if a master controller supports
> memory mapped operation and slave wants to use memcpy in his
> driver(bypassing spi ), then we should have a mean to communicate
> between the
> master and the slave. So, 'spi_master' seems to be the place for me
> for this data,
> which could be parsed in the slave side also.

I would have expected that the address would be returned by the function
that maps the buffer in rather than stored permanently in the master.

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Re: [PATCH 09/17] spi/spi.h: Add "mem" variable in spi master.

[Sourav Poddar]

On Tuesday 26 November 2013 06:50 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 06:35:35PM +0530, Sourav Poddar wrote:
>> On Tuesday 26 November 2013 06:31 PM, Mark Brown wrote:
>>> Is this really generic enough to put here rather than in the driver
>>> data?
>> The thought behind this was that if a master controller supports
>> memory mapped operation and slave wants to use memcpy in his
>> driver(bypassing spi ), then we should have a mean to communicate
>> between the
>> master and the slave. So, 'spi_master' seems to be the place for me
>> for this data,
>> which could be parsed in the slave side also.
> I would have expected that the address would be returned by the function
> that maps the buffer in rather than stored permanently in the master.
Yes, it could be be done the above way. I will change.
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[PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Sourav Poddar]

Idea is to enable memory mapped by default at the end of the probe,
if the control reaches the "transfer" api, then the operation is
not a memory mapped one. Hence, we switch to Normal mode and at the
end of the "transfer" function. switch back to memory mapped mode.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/spi/spi-ti-qspi.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index d21d40d..ba95d64 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -415,6 +415,8 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
 	int status = 0, ret;
 	int frame_length;
 
+	disable_qspi_memory_mapped(qspi);
+
 	/* setup device control reg */
 	qspi->dc = 0;
 
@@ -460,6 +462,8 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
 
 	ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 
+	enable_qspi_memory_mapped(qspi);
+
 	return status;
 }
 
@@ -613,6 +617,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_master;
 
+	enable_qspi_memory_mapped(qspi);
+
 	return 0;
 
 free_master:
-- 
1.7.1

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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 443 bytes --]

On Tue, Nov 26, 2013 at 01:05:08PM +0530, Sourav Poddar wrote:
> Idea is to enable memory mapped by default at the end of the probe,
> if the control reaches the "transfer" api, then the operation is
> not a memory mapped one. Hence, we switch to Normal mode and at the
> end of the "transfer" function. switch back to memory mapped mode.

This doesn't see safe, what happens if something tries to use the map
while a transfer is in progress?

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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Sourav Poddar]

Hi Mark,
On Tuesday 26 November 2013 06:41 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:05:08PM +0530, Sourav Poddar wrote:
>> Idea is to enable memory mapped by default at the end of the probe,
>> if the control reaches the "transfer" api, then the operation is
>> not a memory mapped one. Hence, we switch to Normal mode and at the
>> end of the "transfer" function. switch back to memory mapped mode.
> This doesn't see safe, what happens if something tries to use the map
> while a transfer is in progress?
Transfer gets initiated with the following api "ti_qspi_start_transfer_one".

At the beginning of this api, I am doing a "disable memory mapped", as 
becuase of
the code implemntation, if the control has reaches this api, memory 
mapped is not
the desired operation. Then, at the end of this api after
"spi_finalize_current_message(master)", which indicated the current 
transfer complete, I
issue a end of transfer command. Only after which, I enable memory 
mapped mode again.

So, will the condition you mention above will hit.? Please help me 
understand if i am
missing something?


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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Mark Brown]

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On Thu, Nov 28, 2013 at 10:54:12AM +0530, Sourav Poddar wrote:

> At the beginning of this api, I am doing a "disable memory mapped",
> as becuase of
> the code implemntation, if the control has reaches this api, memory
> mapped is not
> the desired operation. Then, at the end of this api after
> "spi_finalize_current_message(master)", which indicated the current
> transfer complete, I
> issue a end of transfer command. Only after which, I enable memory
> mapped mode again.

> So, will the condition you mention above will hit.? Please help me
> understand if i am
> missing something?

Removing the mapping isn't going to stop another context which has
obtained a handle on the map trying to look at the mapping.

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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Sourav Poddar]

On Thursday 28 November 2013 04:19 PM, Mark Brown wrote:
> On Thu, Nov 28, 2013 at 10:54:12AM +0530, Sourav Poddar wrote:
>
>> At the beginning of this api, I am doing a "disable memory mapped",
>> as becuase of
>> the code implemntation, if the control has reaches this api, memory
>> mapped is not
>> the desired operation. Then, at the end of this api after
>> "spi_finalize_current_message(master)", which indicated the current
>> transfer complete, I
>> issue a end of transfer command. Only after which, I enable memory
>> mapped mode again.
>> So, will the condition you mention above will hit.? Please help me
>> understand if i am
>> missing something?
> Removing the mapping isn't going to stop another context which has
> obtained a handle on the map trying to look at the mapping.
hmm..so the  'memcpy' part should be made atomic.(if possible?).
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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Mark Brown]

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On Thu, Nov 28, 2013 at 04:38:27PM +0530, Sourav Poddar wrote:
> On Thursday 28 November 2013 04:19 PM, Mark Brown wrote:

> >Removing the mapping isn't going to stop another context which has
> >obtained a handle on the map trying to look at the mapping.

> hmm..so the  'memcpy' part should be made atomic.(if possible?).

Or holding the memory region should prevent normal SPI use (so any users
ought to drop the memory region when they don't need it).

I'm still a bit surprised there's no DMA controllers for this...

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Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.

[Sourav Poddar]

On Thursday 28 November 2013 05:29 PM, Mark Brown wrote:
> On Thu, Nov 28, 2013 at 04:38:27PM +0530, Sourav Poddar wrote:
>> On Thursday 28 November 2013 04:19 PM, Mark Brown wrote:
>>> Removing the mapping isn't going to stop another context which has
>>> obtained a handle on the map trying to look at the mapping.
>> hmm..so the  'memcpy' part should be made atomic.(if possible?).
> Or holding the memory region should prevent normal SPI use (so any users
> ought to drop the memory region when they don't need it).
hmm.ok i will unmap the memory region when not in use.
> I'm still a bit surprised there's no DMA controllers for this...
Yes, but thats the truth :(

[PATCH 13/17] drivers: mtd: m25p80: Add api to configure master register.

[Sourav Poddar]

These can be used to fill information needed to configure 
master controller registers.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/mtd/devices/m25p80.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7dc2c14..6a27677 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -490,6 +490,23 @@ static inline int m25p80_dummy_cycles_read(struct m25p *flash)
 }
 
 /*
+ * This API can be used to transfer flash information to
+ * SPI controller which needs some of its registers to get
+ * configured on flash.
+ */
+static void m25p80_fill_flash_information(struct m25p *flash)
+{
+	struct spi_master *master = flash->spi->master;
+	u8 info[4];
+	info[0] = flash->read_opcode;
+	info[1] = flash->program_opcode;
+	info[2] = flash->addr_width;
+	info[3] = m25p80_dummy_cycles_read(flash);
+
+	master->configure_from_slave(flash->spi, info);
+}
+
+/*
  * Read an address range from the flash chip.  The address range
  * may be any size provided it is within the physical boundaries.
  */
-- 
1.7.1

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[PATCH 14/17] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

Adapt driver to do a memory mapped read.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 drivers/mtd/devices/m25p80.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6a27677..b7ed4be 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -514,6 +514,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	size_t *retlen, u_char *buf)
 {
 	struct m25p *flash = mtd_to_m25p(mtd);
+	struct spi_master *master = flash->spi->master;
 	struct spi_transfer t[2];
 	struct spi_message m;
 	uint8_t opcode;
@@ -522,6 +523,14 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
 			__func__, (u32)from, len);
 
+	if (master->mmap) {
+		master->get_buf(master);
+		memcpy(buf, master->mem + from, len);
+		master->put_buf(master);
+		*retlen = len;
+		goto out;
+	}
+
 	spi_message_init(&m);
 	memset(t, 0, (sizeof t));
 
@@ -559,6 +568,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 
 	mutex_unlock(&flash->lock);
 
+out:
 	return 0;
 }
 
@@ -1285,6 +1295,9 @@ static int m25p_probe(struct spi_device *spi)
 		flash->addr_width = 3;
 	}
 
+	if (spi->master->configure_from_slave)
+		m25p80_fill_flash_information(flash);
+
 	dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
 			(long long)flash->mtd.size >> 10);
 
-- 
1.7.1

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[PATCH 15/17] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on dra7.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..2c8753a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	qspi1_pins: pinmux_qspi1_pins {
+		pinctrl-single,pins = <
+			0x4c 0x40001  /* gpmc_a3.qspi1_cs2 */
+			0x50 0x40001  /* gpmc_a4.qspi1_cs3 */
+			0x74 0x40001  /* gpmc_a13.qspi1_rtclk */
+			0x78 0x40001  /* gpmc_a14.qspi1_d3 */
+			0x7c 0x40001  /* gpmc_a15.qspi1_d2 */
+			0x80 0x40001  /* gpmc_a16.qspi1_d1 */
+			0x84 0x40001  /* gpmc_a17.qspi1_d0 */
+			0x88 0x40001  /* qpmc_a18.qspi1_sclk */
+			0xb8 0x60001  /* gpmc_cs2.qspi1_cs0 */
+			0xbc 0x60001  /* gpmc_cs3.qspi1_cs1 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -273,3 +288,20 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_pins>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		qspi: qspi@4b300000 {
+			compatible = "ti,dra7xxx-qspi";
+			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
+					<0x5c000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			num-cs = <4>;
+			interrupts = <0 124 0x4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
-- 
1.7.1

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[PATCH 17/17] Documentation: bindings: ti-qspi: update binding information.

[Sourav Poddar]

These update binding information for ti qspi controller.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
 Documentation/devicetree/bindings/spi/ti_qspi.txt |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641a..53ff791 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,8 @@ TI QSPI controller.
 Required properties:
 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
 - reg: Should contain QSPI registers location and length.
+- reg-names: Should contain the reg names.
+- interrupts: should contain the qspi interrupt number.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - ti,hwmods: Name of the hwmod associated to the QSPI
 
-- 
1.7.1

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[PATCH 10/17] spi/spi.h: Add mmap flag in spi master.

[Sourav Poddar]

Add "mmap" flag which can be used to show that the master
controller supports memory mapped operations.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 include/linux/spi/spi.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 72565ff..9425ea4 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -299,6 +299,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *      to be configured from slave specifics information(typical use case for
  *      SPI flash device).
  * @mem: memory mapped address to be filled by master controller driver.
+ * @mmap: Shows that master controller supports memory mapped operation.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -437,6 +438,7 @@ struct spi_master {
 
 	/* gpio chip select */
 	int			*cs_gpios;
+	bool	mmap;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.1

[PATCH 11/17] spi/qspi: set "mmap" flag to true.

[Sourav Poddar]

Set mmap flag to true to indicate that the qspi controller
supports memory mapped operations.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 10bcb37..d21d40d 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -532,6 +532,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->configure_from_slave = ti_qspi_configure_from_slave;
 	master->get_buf = ti_qspi_get_mem_buf;
 	master->put_buf = ti_qspi_put_mem_buf;
+	master->mmap = true;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

Re: [PATCH 11/17] spi/qspi: set "mmap" flag to true.

[Mark Brown]

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On Tue, Nov 26, 2013 at 01:05:07PM +0530, Sourav Poddar wrote:
> Set mmap flag to true to indicate that the qspi controller
> supports memory mapped operations.

Please combine some of these patches - adding the mmap support and then
separately adding this flag isn't really helping bisection, just have
one patch enabling support for mmap in the driver.  Similarly adding
internal functions to the driver with no users and then separately
adding the users isn't really adding much.

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Re: [PATCH 11/17] spi/qspi: set "mmap" flag to true.

[Sourav Poddar]

On Tuesday 26 November 2013 06:40 PM, Mark Brown wrote:
> On Tue, Nov 26, 2013 at 01:05:07PM +0530, Sourav Poddar wrote:
>> Set mmap flag to true to indicate that the qspi controller
>> supports memory mapped operations.
> Please combine some of these patches - adding the mmap support and then
> separately adding this flag isn't really helping bisection, just have
> one patch enabling support for mmap in the driver.  Similarly adding
> internal functions to the driver with no users and then separately
> adding the users isn't really adding much.
Sure, I will do that in my next version.
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[PATCH 16/17] arm: dts: am43x-epos: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on am43x-epos-evm.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi        |   12 ++++++++++++
 arch/arm/boot/dts/am43x-epos-evm.dts |   28 ++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f1dd131..6ccf5c2 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -663,6 +663,18 @@
 			       <&edma 11>;
 			dma-names = "tx", "rx";
 		};
+
+		qspi: qspi@47900000 {
+			compatible = "ti,am4372-qspi";
+			reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			interrupts = <0 138 0x4>;
+			num-cs = <4>;
+                        status = "disabled";
+                };
 	};
 
 	clocks {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..a037a92 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,17 @@
 				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+				0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
 	};
 
 	matrix_keypad: matrix_keypad@0 {
@@ -184,3 +195,20 @@
 &gpio3 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+	};
+};
-- 
1.7.1

Re: [PATCH 00/17] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Brian,
On Tuesday 26 November 2013 01:04 PM, Sourav Poddar wrote:
> The patch series aims to add memory mapped support for TI qspi
> contoller and also add support for the same in serial flash driver(m25p80).
>
> These feature was added as a part of the series[1]:
> The series[1] add support for quad and memory mapped feature in spi and
> flash driver. Based on Brian Norris suggestion on splitting the quad and
> memory mapped feature, I had sent a seperate series for quad support which
> has beed accepted by Brian.
>
> The $subject patch series takes care of the memory mapped part.
>
> Overview of memory mapped support in qspi:
>   TI qspi controller supports memory mapped read support, switching to which
>   requires  register modifications(qspi registers, control module register for
>   DRA, qspi register for am43x). Once switched, the flash data can be available
>   at a soc specific memory mapped address. For operations in normal mode, we need
>   to keep memory mapped disable.
>
>   Flow of the patch is to keep the memory mapped enable by default in the driver.
>   Whenever Normal spi mode operations are desired, we switch to configuration mode
>   and at the end of it memory mapped is again enabled. There are few function pointers
>   added to fecilitate easy communication between the flash and spi controllers.
>
> Major changes in the $subject patch based on discussion in [1]:
>
> - Feature has been broken down into small meaningfl patches.
> - memcpy is done in flash driver and spi framework is bypassed.
> - configuration of memory mapped spi controller regsiters is done
>    through function calls from flash side.
>
> [1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html
>
>
> Tested on DRA7 board with spansion S25FL256S flash along with some
> internal irq crossbar patches.
> Tested on AM437x epos evm with macronix MX66l51235l flash.
>
> Testing done:
> -Erase the whole flash.
> -write to the flash
> -read back the flash
> - compare the data
>
> Sourav Poddar (17):
>    spi/spi.h: Add get_buf/put_buf support in spi master..
>    spi/spi.h: Add configure from slave support.
>    spi/qspi: parse register by name.
>    spi/qspi: parse control module register.
>    spi/qspi: parse memory map register.
>    spi/qspi: Add support to switc to memory mapped operation.
>    spi/qspi: configure set up register for memory map..
>    spi/qspi: Add api for get_buf/put_buf.
>    spi/spi.h: Add "mem" variable in spi master.
>    spi/spi.h: Add mmap flag in spi master.
>    spi/qspi: set "mmap" flag to true.
>    spi/qspi: convert driver to enable/disable memory mapped..
>    drivers: mtd: m25p80: Add api to configure master register .
>    drivers: mtd: m25p80: Adapt driver to support memory mapped read.
>    arm: dts: dra7: Add qspi device.
>    arm: dts: am43x-epos: Add qspi device.
>    Documentation: bindings: ti-qspi: update binding information.
>
>   Documentation/devicetree/bindings/spi/ti_qspi.txt |    2 +
>   arch/arm/boot/dts/am4372.dtsi                     |   12 ++
>   arch/arm/boot/dts/am43x-epos-evm.dts              |   28 +++++
>   arch/arm/boot/dts/dra7-evm.dts                    |   32 ++++++
>   arch/arm/boot/dts/dra7.dtsi                       |   13 +++
>   drivers/mtd/devices/m25p80.c                      |   30 ++++++
>   drivers/spi/spi-ti-qspi.c                         |  115 ++++++++++++++++++++-
>   include/linux/spi/spi.h                           |   16 +++
>   8 files changed, 246 insertions(+), 2 deletions(-)
>
Gentle ping on this series on mtd side...

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