[PATCH 0/4] spi: spi-ath79: Devicetree support and misc fixes

[PATCH 0/4] spi: spi-ath79: Devicetree support and misc fixes

[Alban Bedel]

Hello all,

this serie add a DT support for the ATH79 SPI controller and fix a few
trivial bugs. While adding DT support we also remove the unused custom
controller data in favor of the generic GPIO based chip select.

The clock patch add the missing clk_un/prepare to fix the warnings once
the platform is moved to the generic clock framework.

Finally the last patch is to ensure that CS_HIGH chips using CS0 get the
proper CS level before the first transfer.

Alban

Alban Bedel (4):
  devicetree: add binding documentation for the AR7100 SPI controller
  spi: spi-ath79: Add device tree support
  spi: spi-ath79: Use clk_prepare_enable and clk_disable_unprepare
  spi: spi-ath79: Set the initial state of CS0

 .../devicetree/bindings/spi/spi-ath79.txt          | 24 +++++++++++++++
 .../include/asm/mach-ath79/ath79_spi_platform.h    |  4 ---
 drivers/spi/spi-ath79.c                            | 34 ++++++++++++++--------
 3 files changed, 46 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt

-- 
2.0.0

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[PATCH 1/4] devicetree: add binding documentation for the AR7100 SPI controller

[Alban Bedel]

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 .../devicetree/bindings/spi/spi-ath79.txt          | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt
new file mode 100644
index 0000000..f1ad9c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-ath79.txt
@@ -0,0 +1,24 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- clocks: phandle to the AHB clock.
+- clock-names: has to be "ahb".
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi@1F000000 {
+		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+		reg = <0x1F000000 0x10>;
+
+		clocks = <&pll 2>;
+		clock-names = "ahb";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
-- 
2.0.0

Re: [PATCH 1/4] devicetree: add binding documentation for the AR7100 SPI controller

[Sergei Shtylyov]

Hello.

On 04/24/2015 05:19 PM, Alban Bedel wrote:

> Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> ---
>   .../devicetree/bindings/spi/spi-ath79.txt          | 24 ++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt

> diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt
> new file mode 100644
> index 0000000..f1ad9c3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-ath79.txt
> @@ -0,0 +1,24 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
> +
> +Required properties:
> +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
> +- reg: Base address and size of the controllers memory area
> +- clocks: phandle to the AHB clock.

    s/to/of/?

> +- clock-names: has to be "ahb".
> +- #address-cells: <1>, as required by generic SPI binding.
> +- #size-cells: <0>, also as required by generic SPI binding.
> +
> +Child nodes as per the generic SPI binding.
> +
> +Example:
> +
> +	spi@1F000000 {

    All lowercase, please.

> +		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
> +		reg = <0x1F000000 0x10>;

    Likewise.

[...]

WBR, Sergei

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[PATCH] devicetree: Misc fix for the AR7100 SPI controller binding

[Alban Bedel]

Fix the clocks property documentation and use lower case for
hex values in the example.

Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
---

This patch can be applied as is or as a fixup to the original patch:
"spi: spi-ath79: add binding documentation for the AR7100 SPI controller"
or I can resend the whole patch/serie if that's preferable.
---
 Documentation/devicetree/bindings/spi/spi-ath79.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt
index f1ad9c3..9c696fa 100644
--- a/Documentation/devicetree/bindings/spi/spi-ath79.txt
+++ b/Documentation/devicetree/bindings/spi/spi-ath79.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
 Required properties:
 - compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
 - reg: Base address and size of the controllers memory area
-- clocks: phandle to the AHB clock.
+- clocks: phandle of the AHB clock.
 - clock-names: has to be "ahb".
 - #address-cells: <1>, as required by generic SPI binding.
 - #size-cells: <0>, also as required by generic SPI binding.
@@ -12,9 +12,9 @@ Child nodes as per the generic SPI binding.
 
 Example:
 
-	spi@1F000000 {
+	spi@1f000000 {
 		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
-		reg = <0x1F000000 0x10>;
+		reg = <0x1f000000 0x10>;
 
 		clocks = <&pll 2>;
 		clock-names = "ahb";
-- 
2.0.0

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[PATCH 3/4] spi: spi-ath79: Use clk_prepare_enable and clk_disable_unprepare

[Alban Bedel]

Clocks should be prepared and unprepared, fix this by using
clk_prepare_enable() and clk_disable_unprepare() instead of
clk_enable() and clk_disable().

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 drivers/spi/spi-ath79.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index 239bc31..b37bedd 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -249,7 +249,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
 		goto err_put_master;
 	}
 
-	ret = clk_enable(sp->clk);
+	ret = clk_prepare_enable(sp->clk);
 	if (ret)
 		goto err_put_master;
 
@@ -273,7 +273,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
 err_disable:
 	ath79_spi_disable(sp);
 err_clk_disable:
-	clk_disable(sp->clk);
+	clk_disable_unprepare(sp->clk);
 err_put_master:
 	spi_master_put(sp->bitbang.master);
 
@@ -286,7 +286,7 @@ static int ath79_spi_remove(struct platform_device *pdev)
 
 	spi_bitbang_stop(&sp->bitbang);
 	ath79_spi_disable(sp);
-	clk_disable(sp->clk);
+	clk_disable_unprepare(sp->clk);
 	spi_master_put(sp->bitbang.master);
 
 	return 0;
-- 
2.0.0

[PATCH 4/4] spi: spi-ath79: Set the initial state of CS0

[Alban Bedel]

The internal chip select CS0 wasn't initialized properly to work with
CS HIGH chips.

Signed-off-by: Alban Bedel <albeu@free.fr>
---
 drivers/spi/spi-ath79.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index b37bedd..bf1f9b3 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -115,6 +115,7 @@ static void ath79_spi_disable(struct ath79_spi *sp)
 
 static int ath79_spi_setup_cs(struct spi_device *spi)
 {
+	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 	int status;
 
 	if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
@@ -132,6 +133,13 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
 
 		status = gpio_request_one(spi->cs_gpio, flags,
 					  dev_name(&spi->dev));
+	} else {
+		if (spi->mode & SPI_CS_HIGH)
+			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+		else
+			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+
+		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
 	}
 
 	return status;
-- 
2.0.0

[PATCH 2/4] spi: spi-ath79: Add device tree support

[Alban Bedel]

Set the OF node of the spi controller and use the generic GPIO based
chip select instead of the custom controller data. As the controller
data isn't used by any board just drop it.

Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
---
 .../mips/include/asm/mach-ath79/ath79_spi_platform.h |  4 ----
 drivers/spi/spi-ath79.c                              | 20 +++++++++++---------
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
index aa2283e..aa71216 100644
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
@@ -16,8 +16,4 @@ struct ath79_spi_platform_data {
 	unsigned	num_chipselect;
 };
 
-struct ath79_spi_controller_data {
-	unsigned	gpio;
-};
-
 #endif /* _ATH79_SPI_PLATFORM_H */
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index b02eb4a..239bc31 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -79,10 +79,8 @@ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
 	}
 
 	if (spi->chip_select) {
-		struct ath79_spi_controller_data *cdata = spi->controller_data;
-
 		/* SPI is normally active-low */
-		gpio_set_value(cdata->gpio, cs_high);
+		gpio_set_value(spi->cs_gpio, cs_high);
 	} else {
 		if (cs_high)
 			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
@@ -117,11 +115,9 @@ static void ath79_spi_disable(struct ath79_spi *sp)
 
 static int ath79_spi_setup_cs(struct spi_device *spi)
 {
-	struct ath79_spi_controller_data *cdata;
 	int status;
 
-	cdata = spi->controller_data;
-	if (spi->chip_select && !cdata)
+	if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
 		return -EINVAL;
 
 	status = 0;
@@ -134,7 +130,7 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
 		else
 			flags |= GPIOF_INIT_HIGH;
 
-		status = gpio_request_one(cdata->gpio, flags,
+		status = gpio_request_one(spi->cs_gpio, flags,
 					  dev_name(&spi->dev));
 	}
 
@@ -144,8 +140,7 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
 static void ath79_spi_cleanup_cs(struct spi_device *spi)
 {
 	if (spi->chip_select) {
-		struct ath79_spi_controller_data *cdata = spi->controller_data;
-		gpio_free(cdata->gpio);
+		gpio_free(spi->cs_gpio);
 	}
 }
 
@@ -217,6 +212,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
 	}
 
 	sp = spi_master_get_devdata(master);
+	master->dev.of_node = pdev->dev.of_node;
 	platform_set_drvdata(pdev, sp);
 
 	pdata = dev_get_platdata(&pdev->dev);
@@ -301,12 +297,18 @@ static void ath79_spi_shutdown(struct platform_device *pdev)
 	ath79_spi_remove(pdev);
 }
 
+static const struct of_device_id ath79_spi_of_match[] = {
+	{ .compatible = "qca,ar7100-spi", },
+	{ },
+};
+
 static struct platform_driver ath79_spi_driver = {
 	.probe		= ath79_spi_probe,
 	.remove		= ath79_spi_remove,
 	.shutdown	= ath79_spi_shutdown,
 	.driver		= {
 		.name	= DRV_NAME,
+		.of_match_table = ath79_spi_of_match,
 	},
 };
 module_platform_driver(ath79_spi_driver);
-- 
2.0.0

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Re: [PATCH 0/4] spi: spi-ath79: Devicetree support and misc fixes

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 382 bytes --]

On Fri, Apr 24, 2015 at 04:19:20PM +0200, Alban Bedel wrote:
> Hello all,
> 
> this serie add a DT support for the ATH79 SPI controller and fix a few
> trivial bugs. While adding DT support we also remove the unused custom
> controller data in favor of the generic GPIO based chip select.

Applied, thanks.  Please use subject lines reflecting the style for the
subsystem.

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