From mboxrd@z Thu Jan 1 00:00:00 1970 From: Florian Fainelli Subject: Re: [PATCH, V4, 2/5] spi: bcm-qspi: Add SPI flash and MSPI driver Date: Wed, 22 Jun 2016 10:13:00 -0700 Message-ID: <576AC71C.9090202@gmail.com> References: <1466197433-11290-1-git-send-email-kdasu.kdev@gmail.com> <1466197433-11290-2-git-send-email-kdasu.kdev@gmail.com> <20160622160726.GQ28202@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, vikram.prakash-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, andy.fung-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, Yendapally Reddy Dhananjaya Reddy To: Mark Brown , Kamal Dasu Return-path: In-Reply-To: <20160622160726.GQ28202-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: On 06/22/2016 09:07 AM, Mark Brown wrote: >> + /* >> + * MIPS endianness is configured by boot strap, which also reverses all >> + * bus endianness (i.e., big-endian CPU + big endian bus ==> native >> + * endian I/O). >> + * >> + * Other architectures (e.g., ARM) either do not support big endian, or >> + * else leave I/O in little endian mode. >> + */ >> + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) >> + return ioread32be(qspi->base[type] + offset); >> + else >> + return readl_relaxed(qspi->base[type] + offset); > > Just put this in the DT like we do for other MIPS IPs. As in, putting a native-endian property for this node, right? -- Florian -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html