From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 227A412B69 for ; Tue, 19 Dec 2023 08:26:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RZFBePNl" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-3365f1326e4so2963136f8f.1 for ; Tue, 19 Dec 2023 00:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702974383; x=1703579183; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=44tWTX/RSFAs3xTgaKfAwubj6hvu6hnjcH+agLDrfuI=; b=RZFBePNlvKK1/SmZLxoV0uLC3wND4aSou+pK00QdXHajnjSqDvBfImhZs9HW13G0l5 63FDyumdA7ivqVvtgOzFA/1UmqNh/e4ZacC+kIatzicFjLQ/ZnHK0Lpr0yldn/Kj5QMa uZh8t4eGpEgBNKAOareAjep+3eGko73g0/O6+a/AYoGPNHr5rMdNRV6WtRiPCX/5iV9a 9iVq2vghUkizJIr5tB7JIDs6sSEVPj7LXHsPP6eFm5Pz764AcSltwxHoeWKEyHHrEl5q RSc+IL1n2/JGkK8X910oLJMrNK78RSHxs3P4QWrf88fuxGBMfRSCmZGggJZb7TfA/sYN oY0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702974383; x=1703579183; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=44tWTX/RSFAs3xTgaKfAwubj6hvu6hnjcH+agLDrfuI=; b=W82l4bVLOv5sGLM6J2jo1oByWr9n1lSEAPSdOwkaaWezxppRATmv/25miF9tPis/Iq ZK6qhPoBGiZcKEcwPLC6u1J/Jqfu/y9UqVFYuyKAGwaRkv+D4lD2Q+K2XO6CJfPmnKJ9 UF+lMTWyciHkn3RrsHvsJLedpau8M895nbGiFP9Lj+oIIjBekZG7yh4+Pa7i9HA6Q2Nc RNXl2OdTrUlgypT5cbvEhr1qRKRo4dUjN0/2yTncDfLzoqNKSyZKOg+R1fjXNEYaRkzZ 66mAJMvjVppdYcVu0QMiQZhpmgkzf6hPwM0ru3hPLF/n7cSwsxj+rpt9EsU3QhqKxABL 2n9Q== X-Gm-Message-State: AOJu0YwbTUb/Y+Rg9H8BCCSClxrI3IG62riecaIPmtfTFKwXZdCrn+Vd kEWK078fwByMC3iX1KIEbH6B52UBZayQogm9xTk= X-Google-Smtp-Source: AGHT+IFhixtyy2y9O5fWKScajlDY2zaXPIfDPrVd3MMvihiJ4///TFioM3EVhUMMvTdIrJts+xU3cQ== X-Received: by 2002:a5d:6801:0:b0:336:6e12:7c62 with SMTP id w1-20020a5d6801000000b003366e127c62mr861872wru.110.1702974383315; Tue, 19 Dec 2023 00:26:23 -0800 (PST) Received: from [192.168.2.173] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id d5-20020a5d5385000000b0033662cf5e51sm6719841wrv.93.2023.12.19.00.26.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Dec 2023 00:26:22 -0800 (PST) Message-ID: <576d56ed-d24b-40f9-9ae4-a02c50eea2ab@linaro.org> Date: Tue, 19 Dec 2023 10:26:20 +0200 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor Content-Language: en-US To: "Mahapatra, Amit Kumar" , "broonie@kernel.org" , "pratyush@kernel.org" , "miquel.raynal@bootlin.com" , "richard@nod.at" , "vigneshr@ti.com" , "sbinding@opensource.cirrus.com" , "lee@kernel.org" , "james.schulman@cirrus.com" , "david.rhodes@cirrus.com" , "rf@opensource.cirrus.com" , "perex@perex.cz" , "tiwai@suse.com" Cc: "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "michael@walle.cc" , "linux-mtd@lists.infradead.org" , "nicolas.ferre@microchip.com" , "alexandre.belloni@bootlin.com" , "claudiu.beznea@tuxon.dev" , "Simek, Michal" , "linux-arm-kernel@lists.infradead.org" , "alsa-devel@alsa-project.org" , "patches@opensource.cirrus.com" , "linux-sound@vger.kernel.org" , "git (AMD-Xilinx)" , "amitrkcian2002@gmail.com" References: <20231125092137.2948-1-amit.kumar-mahapatra@amd.com> <20231125092137.2948-8-amit.kumar-mahapatra@amd.com> <5a6f6764-6779-42b0-b6c6-3f638b85ef78@linaro.org> From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 15.12.2023 13:20, Mahapatra, Amit Kumar wrote: > Hello Tudor, > Hi! >> -----Original Message----- >> From: Tudor Ambarus >> Sent: Friday, December 15, 2023 4:03 PM >> To: Mahapatra, Amit Kumar ; >> broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; >> richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; >> lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; >> rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com >> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; michael@walle.cc; >> linux-mtd@lists.infradead.org; nicolas.ferre@microchip.com; >> alexandre.belloni@bootlin.com; claudiu.beznea@tuxon.dev; Simek, Michal >> ; linux-arm-kernel@lists.infradead.org; alsa- >> devel@alsa-project.org; patches@opensource.cirrus.com; linux- >> sound@vger.kernel.org; git (AMD-Xilinx) ; >> amitrkcian2002@gmail.com >> Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support >> in spi-nor >> >> >> >> On 12/15/23 10:02, Mahapatra, Amit Kumar wrote: >>> Hello Tudor, >> >> Hi, >> >>> >>>> -----Original Message----- >>>> From: Tudor Ambarus >>>> Sent: Friday, December 15, 2023 1:40 PM >>>> To: Mahapatra, Amit Kumar ; >>>> broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; >>>> richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; >>>> lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; >>>> rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com >>>> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; >>>> michael@walle.cc; linux-mtd@lists.infradead.org; >>>> nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com; >>>> claudiu.beznea@tuxon.dev; Simek, Michal ; >>>> linux- arm-kernel@lists.infradead.org; alsa-devel@alsa-project.org; >>>> patches@opensource.cirrus.com; linux-sound@vger.kernel.org; git (AMD- >>>> Xilinx) ; amitrkcian2002@gmail.com >>>> Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories >>>> support in spi-nor >>>> >>>> >>>> >>>> On 15.12.2023 09:55, Mahapatra, Amit Kumar wrote: >>>>>> Thanks! Can you share with us what flashes you used for testing in >>>>>> the stacked and parallel configurations? >>>>> I used SPI-NOR QSPI flashes for testing stacked and parallel. >>>> >>>> I got that, I wanted the flash name or device ID. >>> >>> N25Q00A, MX66U2G45G, IS25LP01G & W25H02JV are some of the QSPI >> flashes >>> on which we tested. Additionally, we conducted tests on over 30 >>> different QSPI flashes from four distinct vendors (Miron, Winbond, >> Macronix, and ISSI). >>> >> >> Great. >> >>>> What I'm interested is if each flash is in its own package. Are they? >>> >>> I'm sorry, but I don't quite understand what you mean by "if each >>> flash in its own package." >>> >> >> There are flashes that are stacked at the physical level. It's a single flash with >> multiple dies, that are all under a single physical package. > > Got it. The W25H02JV QSPI flash I mentioned earlier is a device with > with four dies that are stacked at the physical level. > >> >> As I understand, your stacked flash model is at logical level. You have >> 2 flashes each in its own package. 2 different entities. Is my understanding >> correct? > > Yes, that’s correct. > > I'd like to contribute to your earlier point regarding the placement of > the stacked layer. As you correctly highlighted, it should be in the > spi-mem generic layer. For instance, when a read/write operation extends > across multiple flashes (whether SPI-NOR or SPI-NAND), the stacked layer > must handle the flash crossover. This requires setting the appropriate CS > index in mem->spi->cs_index_mask to select the correct slave device and > updating the data buffer, address & data length in spi_mem_op struct > variable. Does this align with your understanding? > This was the initial idea, yes, but we'll have to see how mtd concat fits in. Maybe the abstraction can be made at the mtd level, which I suspect mtd concat does. I have to read that driver, never opened it. Something else to consider: I see that Micron has a twin quad mode: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25t/generation-b/mt25t_qljs_l_512_xba_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500 The micron's "Separate Chip-Select and Clock Signals" resembles the AMD's dual parallel 8-bit. Micron's "Shared Chip-Select and Clock Signals" differs from the AMD's stacked mode, as Micron uses DQ[3:0] and DQ[7:4], whereas AMD considers both as DQ[3:0]. I had a short chat with Michael and he highlighted that instead of the parallel mode, one would be better of with an octal device. I wonder whether the quad parallel is worth the effort. I see AMD can select either quad (single/stacked/parallel) or octal (single/stacked). Is the parallel mode considered obsolete for new IPs? Cheers, ta