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[82.149.1.233]) by smtp.gmail.com with ESMTPSA id a23-20020a05600c225700b003fc01495383sm2418619wmm.6.2023.08.02.12.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 12:50:44 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Maxim Kiselev Cc: linux-spi@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Samuel Holland , Mark Brown , Cristian Ciocaltea , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port Date: Wed, 02 Aug 2023 21:50:39 +0200 Message-ID: <5956489.lOV4Wx5bFT@jernej-laptop> In-Reply-To: References: <20230624131632.2972546-1-bigunclemax@gmail.com> <10311404.nUPlyArG6x@jernej-laptop> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Dne ponedeljek, 31. julij 2023 ob 17:22:11 CEST je Maxim Kiselev napisal(a): > =D0=BF=D0=BD, 31 =D0=B8=D1=8E=D0=BB. 2023=E2=80=AF=D0=B3. =D0=B2 01:30, J= ernej =C5=A0krabec : > > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a= ): > > > Add pinmux node that describes pins on PC port which required for > > > QSPI mode. > > >=20 > > > Signed-off-by: Maksim Kiselev > > > --- > > >=20 > > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > >=20 > > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > > > 1bb1e5cae602..9f754dd03d85 100644 > > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { > > >=20 > > > pins =3D "PB6", "PB7"; > > > function =3D "uart3"; > > > =20 > > > }; > > >=20 > > > + > > > + /omit-if-no-ref/ > > > + qspi0_pc_pins: qspi0-pc-pins { > > > + pins =3D "PC2", "PC3", "PC4", "PC5", > >=20 > > "PC6", > >=20 > > > + "PC7"; > > > + function =3D "spi0"; > > > + }; > >=20 > > Sorry for late review, but it seems I'm missing something. D1 manual sa= ys > > those are pins for ordinary SPI, with HOLD and WP signals. Can they be > > repurposed for quad SPI? >=20 > Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI > Quad-Input/Quad-Output Mode): > "Using the quad mode allows data to be transferred to or from the > device at 4 times the rate of standard single mode, the data can be > read > at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 > (HOLD#)) at the same time." Alright then. Acked-by: Jernej Skrabec Best regards, Jernej