From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BD3C001DF for ; Thu, 6 Jul 2023 09:26:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232135AbjGFJ02 (ORCPT ); Thu, 6 Jul 2023 05:26:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230477AbjGFJ00 (ORCPT ); Thu, 6 Jul 2023 05:26:26 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE5691BF0; Thu, 6 Jul 2023 02:25:56 -0700 (PDT) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3668EjRL026984; Thu, 6 Jul 2023 11:25:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=7t4eCU5gGbd6E2c3Byzad523u0UnY/0NWeRLFMO8wqQ=; b=oOHQUk7YHvsQeSB7NLsvfkez0kTZlUCcLBgh3hS4SMD5Wr3XtDTxiKvSKowNqENq4C8s /288tIqKzXTGt4S2InHB2hb0Amk1CNtGQGYBfWaqN77e7cTrA1nCFp/hXvhbko3GdqKF L/MzEPCBqP4GZU1Fn/yzQ5JE4cj8OgCenJ0wWY5nRviDPqiXVJho5qJfaAY9qEtW3ldq WNfUylY6/Hwr6gUEHKjKBvvikQWSeI38uHh3/etreV3Px9tW0l50odh6QdLz+VrpwnEn 3Em2pZ9kmrlRUa/Y7HiINICLumd7trhKCCWuff7jg/l/hOAVnY6ZeQv4znQLx1ghbUAx 6w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3rnsxd0je3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Jul 2023 11:25:24 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BB767100052; Thu, 6 Jul 2023 11:25:21 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C615521685E; Thu, 6 Jul 2023 11:25:21 +0200 (CEST) Received: from [10.201.21.122] (10.201.21.122) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 6 Jul 2023 11:25:19 +0200 Message-ID: <61d93738-4ffd-411d-d32c-912c14eea56d@foss.st.com> Date: Thu, 6 Jul 2023 11:25:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 07/10] arm64: dts: st: add RIFSC as a domain controller for STM32MP25x boards To: Gatien Chevallier , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , References: <20230705172759.1610753-1-gatien.chevallier@foss.st.com> <20230705172759.1610753-8-gatien.chevallier@foss.st.com> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <20230705172759.1610753-8-gatien.chevallier@foss.st.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.201.21.122] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-06_06,2023-07-06_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi Gatien On 7/5/23 19:27, Gatien Chevallier wrote: > RIFSC is a firewall controller. Change its compatible so that is matches > the documentation and reference RIFSC as a feature-domain-controller. > > Signed-off-by: Gatien Chevallier > --- > arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi > index 5268a4321841..62101084cab8 100644 > --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi > @@ -106,17 +106,20 @@ soc@0 { > ranges = <0x0 0x0 0x0 0x80000000>; > > rifsc: rifsc-bus@42080000 { > - compatible = "simple-bus"; > + compatible = "st,stm32mp25-rifsc"; You could keep "simple-bus" compatible (in second position). In case of the RIFSC is not probed, the platform will be able to boot. If you agree you can use the same for ETZPC. Cheers Alex > reg = <0x42080000 0x1000>; > #address-cells = <1>; > #size-cells = <1>; > ranges; > + feature-domain-controller; > + #feature-domain-cells = <1>; > > usart2: serial@400e0000 { > compatible = "st,stm32h7-uart"; > reg = <0x400e0000 0x400>; > interrupts = ; > clocks = <&ck_flexgen_08>; > + feature-domains = <&rifsc 32>; > status = "disabled"; > }; > };