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Message-ID: <6e0bd3a8-65a4-2066-79f2-d59e6bb2b7ea@linux.intel.com>
Date:   Thu, 30 Jun 2022 10:03:46 +0300
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Subject: Re: [PATCH] spi: pxa2xx: Add support for Intel Meteor Lake PCH-P
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To:     Andy Shevchenko <andy.shevchenko@gmail.com>
Cc:     linux-spi <linux-spi@vger.kernel.org>,
        Mark Brown <broonie@kernel.org>,
        Daniel Mack <daniel@zonque.org>,
        Haojian Zhuang <haojian.zhuang@gmail.com>,
        Robert Jarzmik <robert.jarzmik@free.fr>,
        Ap Kamal <kamal.ap@intel.com>
References: <20220629120700.620108-1-jarkko.nikula@linux.intel.com>
 <CAHp75VdhGDR0cGt2Aky=sRRDB=u4mwxWZgQ+DGL08QZFBMKiAg@mail.gmail.com>
From:   Jarkko Nikula <jarkko.nikula@linux.intel.com>
In-Reply-To: <CAHp75VdhGDR0cGt2Aky=sRRDB=u4mwxWZgQ+DGL08QZFBMKiAg@mail.gmail.com>
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On 6/29/22 18:35, Andy Shevchenko wrote:
> On Wed, Jun 29, 2022 at 2:09 PM Jarkko Nikula
> <jarkko.nikula@linux.intel.com> wrote:
>>
>> Add support for LPSS SPI on Intel Meteor Lake PCH-P. It has three
>> controllers each having two chip selects.
>>
>> This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect
>> PCI ID of 3rd controller.
> 
> With PCH removed from the commit message (including subject)
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> 
Hmm, right. Thanks Andy, Meteor Lake -P seems to integrate PCH die 
functionality into a SoC.

Jarkko