From mboxrd@z Thu Jan 1 00:00:00 1970 From: Florian Fainelli Subject: Re: [PATCH 0/7] Raspberry Pi spi0 improvements Date: Tue, 13 Nov 2018 21:12:01 -0800 Message-ID: <7ba12f83-a78f-4827-b962-4b08cad341fa@gmail.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Mathias Duckeck , Frank Pavlic , Noralf Tronnes , linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Lukas Wunner , Mark Brown , Eric Anholt , Stefan Wahren Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-rpi-kernel" Errors-To: linux-rpi-kernel-bounces+glkr-linux-rpi-kernel=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-spi.vger.kernel.org On 11/7/2018 11:06 PM, Lukas Wunner wrote: > Here's a first batch of improvements for the spi0 master on the > Raspberry Pi. The meat of the series is in its last two patches: > > * Patch [6/7] allows DMA for transfer buffers starting at an offset not a > multiple of 4. This overcomes a limitation affecting Ethernet drivers > such as ks8851 which call netdev_alloc_skb_ip_align() to allocate > deliberately unaligned receive buffers. > > * Patch [7/7] speeds up PIO transfers by not polling the RX FIFO when it > is known to contain data, or the TX FIFO when it is known to have free > space. > > The preceding patches fix rarely encountered bugs, remove obsolete code > and add documentation. > > The series has been tested extensively on the "Revolution Pi" family of > open source PLCs (https://revolution.kunbus.com/), but further testing > would be welcome to raise the confidence. Do you have some performance numbers that you could share before/after, e.g: transfer latencies, number of interrupts and pure throughput? Thanks for doing this work! -- Florian