From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, Steam Lin <stlin2@winbond.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Sanjay R Mehta <sanju.mehta@amd.com>, Han Xu <han.xu@nxp.com>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Haibo Chen <haibo.chen@nxp.com>,
Yogesh Gaur <yogeshgaur.83@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 22/24] mtd: spinand: Add support for read DTR operations
Date: Fri, 13 Dec 2024 13:08:45 +0100 [thread overview]
Message-ID: <87ed2blr8y.fsf@bootlin.com> (raw)
In-Reply-To: <589d95d3-9153-475b-86f7-886ec41cd4f4@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 14:35:23 +0000")
Hi Tudor,
On 11/11/2024 at 14:35:23 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
> On 10/25/24 5:14 PM, Miquel Raynal wrote:
>> + SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1),
>
> do we want some names to these hex values?
I honestly don't think we do because it would be totally redundant with
the macro name, ie.
+#define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
+ SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
+ SPI_MEM_OP_MAX_FREQ(freq))
is IMHO better than
+#define SPINAND_PAGE_READ_FROM_CACHE_DTR_OPCODE 0x0d
+#define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINAND_PAGE_READ_FROM_CACHE_DTR_OPCODE, 1), \
+ SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
+ SPI_MEM_OP_MAX_FREQ(freq))
next prev parent reply other threads:[~2024-12-13 12:08 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-25 16:14 [PATCH 00/24] spi-nand/spi-mem DTR support Miquel Raynal
2024-10-25 16:14 ` [PATCH 01/24] spi: spi-mem: Extend spi-mem operations with a per-operation maximum frequency Miquel Raynal
2024-10-30 20:52 ` Han Xu
2024-10-31 6:45 ` Tudor Ambarus
2024-11-11 13:07 ` Tudor Ambarus
2024-12-13 10:46 ` Miquel Raynal
2024-12-18 8:07 ` Tudor Ambarus
2024-12-18 9:37 ` Miquel Raynal
2024-12-18 10:03 ` Tudor Ambarus
2024-12-18 10:13 ` Tudor Ambarus
2024-12-23 19:08 ` Miquel Raynal
2024-11-25 16:05 ` Pratyush Yadav
2024-10-25 16:14 ` [PATCH 02/24] spi: spi-mem: Add a new controller capability Miquel Raynal
2024-10-28 21:10 ` Mark Brown
2024-11-01 20:17 ` Mark Brown
2024-11-07 10:40 ` Miquel Raynal
2024-11-07 17:15 ` Mark Brown
2024-11-08 8:55 ` Miquel Raynal
2024-11-08 12:59 ` Mark Brown
2024-11-11 13:18 ` Tudor Ambarus
2024-12-13 11:00 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches Miquel Raynal
2024-11-11 13:36 ` Tudor Ambarus
2024-12-13 11:20 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 04/24] spi: amlogic-spifc-a1: " Miquel Raynal
2024-11-11 13:42 ` Tudor Ambarus
2024-12-13 11:44 ` Miquel Raynal
2024-12-18 8:09 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 05/24] spi: cadence-qspi: " Miquel Raynal
2024-11-11 13:50 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 06/24] spi: dw: " Miquel Raynal
2024-11-11 14:05 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 07/24] spi: fsl-qspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 08/24] spi: microchip-core-qspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 09/24] spi: mt65xx: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 10/24] spi: mxic: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 11/24] spi: nxp-fspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 12/24] spi: rockchip-sfc: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 13/24] spi: spi-sn-f-ospi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 14/24] spi: spi-ti-qspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 15/24] spi: zynq-qspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 16/24] spi: zynqmp-gqspi: " Miquel Raynal
2024-10-25 16:14 ` [PATCH 17/24] mtd: spinand: Create distinct fast and slow read from cache variants Miquel Raynal
2024-11-11 14:14 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 18/24] mtd: spinand: Add an optional frequency to read from cache macros Miquel Raynal
2024-11-11 14:17 ` Tudor Ambarus
2024-12-13 11:56 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 19/24] mtd: spinand: winbond: Fix the *JW chip definitions Miquel Raynal
2024-11-11 14:27 ` Tudor Ambarus
2024-12-18 8:16 ` Tudor Ambarus
2024-12-18 9:34 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 20/24] spi: spi-mem: Reorder SPI_MEM_OP_CMD internals Miquel Raynal
2024-11-11 14:32 ` Tudor Ambarus
2024-12-13 12:05 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 21/24] spi: spi-mem: Create macros for DTR operation Miquel Raynal
2024-10-25 16:14 ` [PATCH 22/24] mtd: spinand: Add support for read DTR operations Miquel Raynal
2024-11-11 14:35 ` Tudor Ambarus
2024-12-13 12:08 ` Miquel Raynal [this message]
2024-12-18 8:10 ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 23/24] mtd: spinand: winbond: Add comment about naming Miquel Raynal
2024-11-11 14:38 ` Tudor Ambarus
2024-11-13 9:46 ` Tudor Ambarus
2024-12-13 12:25 ` Miquel Raynal
2024-12-18 8:14 ` Tudor Ambarus
2024-12-18 9:33 ` Miquel Raynal
2024-12-18 10:21 ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations Miquel Raynal
2024-11-11 14:40 ` Tudor Ambarus
2024-12-23 18:22 ` Miquel Raynal
2024-12-24 9:38 ` Miquel Raynal
2025-01-10 15:47 ` (subset) [PATCH 00/24] spi-nand/spi-mem DTR support Mark Brown
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