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bh=nFxrTARUlK2wFNTl5JJRwfbFdvOaKS20BeXfCwf1OTM=; b=WbVJvmqx5SngaVM6UbdN+k9MvlZmejh+STd37xHqMa6/V80ztCv5TTyvQqSF2ZFbZuwKLG wqcf/iCEFmf8tLYq3LMumYMnGDFOseajphKL6i+k31pj7vzXlinRSTRo8CT9Z0F1SB40zI BHSk0xRU9k/soVzGY9kc3SAipmmXKrorQxSmg2aGvmDWSBguOJBCOn407tmRTQoOfqXv0n d9NWSnlxHF7WhTkWf8Qm1B+4bSnL3GejLkgtR1fC3GEQrtmP0adKgUX/P4EW0pMh7CgfPj NHTpSKDUXR1oQCOIhrvdO+6740uBOxG+S7nZM5LxV3WNBvF8uWtl1jPLG7wn7g== From: Miquel Raynal To: Md Sadre Alam Cc: Gabor Juhos , Mark Brown , Manivannan Sadhasivam , Richard Weinberger , Vignesh Raghavendra , Varadarajan Narayanan , Sricharan Ramabadhran , , , , Subject: Re: [PATCH next 2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength In-Reply-To: <007881c9-e03c-1473-d8eb-53fbad8c6a8e@quicinc.com> (Md Sadre Alam's message of "Tue, 13 May 2025 21:05:09 +0530") References: <20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com> <20250502-qpic-snand-8bit-ecc-v1-2-95f3cd08bbc5@gmail.com> <8aa3d4da-da3e-2af4-e0f9-cd56d6259d8f@quicinc.com> <878qn2nsa0.fsf@bootlin.com> <16195524-1f31-4968-a3fd-f3d24f1c4223@gmail.com> <87msbhezjf.fsf@bootlin.com> <007881c9-e03c-1473-d8eb-53fbad8c6a8e@quicinc.com> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Fri, 16 May 2025 16:14:00 +0200 Message-ID: <87frh4ej87.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdefuddvleeiucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufgjfhgffffkgggtgfesthhqredttderjeenucfhrhhomhepofhiqhhuvghlucftrgihnhgrlhcuoehmihhquhgvlhdrrhgrhihnrghlsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeffgefhjedtfeeigeduudekudejkedtiefhleelueeiueevheekvdeludehiedvfeenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdpmhgrihhlfhhrohhmpehmihhquhgvlhdrrhgrhihnrghlsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopeduvddprhgtphhtthhopehquhhitggpmhgurghlrghmsehquhhitghinhgtrdgtohhmpdhrtghpthhtohepjhegghekhiejsehgmhgrihhlrdgtohhmpdhrtghpthhtohepsghrohhonhhivgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepmhgrnhhivhgrnhhnrghnrdhsrgguhhgrshhivhgrmheslhhinhgrrhhordhorhhgpdhrtghpthhtoheprhhitghhrghrugesnhhougdrrghtpdhrtghpthhto hepvhhighhnvghshhhrsehtihdrtghomhdprhgtphhtthhopehquhhitggpvhgrrhgruggrsehquhhitghinhgtrdgtohhmpdhrtghpthhtohepqhhuihgtpghsrhhitghhrghrrgesqhhuihgtihhntgdrtghomh X-GND-Sasl: miquel.raynal@bootlin.com >>> Interestingly enough, it reports the correct number of bit errors now. >>> For me it seems, that the hardware reports the number of the corrected >>> *bytes* instead of the corrected *bits*. >> I doubt that, nobody counts bytes of errors. >> You results are surprising. I initially though in favour of a software >> bug, but then it looks even weirder than that. Alam? > I have checked with HW team , the QPIC ECC HW engine reports the bit > error byte wise not bit wise. > > e.g > Byte0 --> 2-bitflips --> QPIC ECC counts 1 only > Byte1 --> 3-bitflips --> QPIC ECC counts 1 only > Byte2 --> 1-bitflips --> QPIC ECC counts 1 only > Byte3 --> 4-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) > Byte4 --> 6-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) > > Hope this can clearify the things now. o_O ???? How is that even useful? This basically means UBI will never refresh the data because we will constantly underestimate the number of bitflips! We need to know the actual number, this averaging does not make any sense for Linux. Is there another way to get the raw number of bitflips? Thanks, Miqu=C3=A8l