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Mon, 24 Aug 2026 06:42:00 -0700 (PDT) X-Received: by 2002:a17:90b:1b41:b0:383:5a16:bd70 with SMTP id 98e67ed59e1d1-395c39f97e8mr42709251a91.16.1787578919646; Mon, 24 Aug 2026 06:41:59 -0700 (PDT) Received: from [10.217.218.158] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395e42d6139sm10107597a91.0.2026.08.24.06.41.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Aug 2026 06:41:58 -0700 (PDT) Message-ID: <8af7a34a-da4f-492f-a51c-cc420edc5e6e@oss.qualcomm.com> Date: Mon, 24 Aug 2026 19:11:51 +0530 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Praveen Talari , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-0-61171ab1cdce@oss.qualcomm.com> <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com> Content-Type: text/plain; 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resources are instead managed by firmware via a genpd performance > domain. The I2C driver therefore relies on geni_se_set_rate() to apply the > fixed 19.2 MHz source clock frequency expected by the SCL divider and somewhere it's 32 MHz also and this may change too ? > counter values programmed by qcom_geni_i2c_conf(). > > Call geni_se_set_rate() directly from qcom_geni_i2c_conf() so the > configured frequency is applied to the correct device (the perf domain > device on the firmware-managed path, or se->dev otherwise) without the I2C > driver needing to know which resources_init() variant is in use. > > Drop the now-unused set_rate field from struct geni_i2c_desc, the > geni_se_set_perf_opp() usage on the SA8255P variant, and the unused freq > parameter from qcom_geni_i2c_conf(). > > Signed-off-by: Praveen Talari > --- > drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index a23554d101fd..4561e2d235d5 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -213,11 +213,11 @@ static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) > return -EINVAL; > } > > -static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) > +static int qcom_geni_i2c_conf(struct geni_se *se) > { > struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev); > const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; > - u32 val; > + u32 val, ret; > > writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); > > @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) > itr->clk_div, itr->t_high_cnt, > itr->t_low_cnt, itr->t_cycle_cnt); > > + ret = geni_se_set_rate(&gi2c->se, 19200000); hard code ? May work currently, but if higher frequency support added, source may change. Also you have added in commit message, but add a comment also here. > + if (ret) > + return ret; > + > return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, > Bps_to_icc(gi2c->clk_freq_out)); > } [...]