From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Md Sadre Alam <quic_mdalam@quicinc.com>,
agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org,
conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
broonie@kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
quic_srichara@quicinc.com, qpic_varada@quicinc.com
Subject: Re: [RFC PATCH 5/5] arm64: dts: qcom: ipq9574: Add support for SPI nand
Date: Tue, 31 Oct 2023 16:27:13 +0100 [thread overview]
Message-ID: <8be3b4f4-f3d1-41c8-bd4a-90adf1a02ea6@linaro.org> (raw)
In-Reply-To: <20231031120307.1600689-6-quic_mdalam@quicinc.com>
On 31.10.2023 13:03, Md Sadre Alam wrote:
> Add support for QPIC SPI NAND for IPQ9574
>
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 56 ++++++++++-----------
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 30 ++++++++++-
> 2 files changed, 57 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> index 1bb8d96c9a82..5e4200edb873 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> @@ -15,48 +15,48 @@ / {
> compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> };
>
> -&sdhc_1 {
> - pinctrl-0 = <&sdc_default_state>;
> - pinctrl-names = "default";
> - mmc-ddr-1_8v;
> - mmc-hs200-1_8v;
> - mmc-hs400-1_8v;
> - mmc-hs400-enhanced-strobe;
> - max-frequency = <384000000>;
> - bus-width = <8>;
> - status = "okay";
> -};
How is removing SDHCI related to adding support for SPI NAND flash?
You must explain your changes in the commit message.
> -
> &tlmm {
> - sdc_default_state: sdc-default-state {
> - clk-pins {
> + qspi_nand_pins: qspi_nand_pins {
node names (between : and {) must not include underscores, use
hyphens instead
> + spi_clock {
> pins = "gpio5";
> - function = "sdc_clk";
> + function = "qspi_clk";
> drive-strength = <8>;
> bias-disable;
> };
>
> - cmd-pins {
> + qspi_cs {
> pins = "gpio4";
> - function = "sdc_cmd";
> + function = "qspi_cs";
> drive-strength = <8>;
> bias-pull-up;
> };
>
> - data-pins {
> - pins = "gpio0", "gpio1", "gpio2",
> - "gpio3", "gpio6", "gpio7",
> - "gpio8", "gpio9";
> - function = "sdc_data";
> + qspi_data {
> + pins = "gpio0", "gpio1", "gpio2";
> + function = "qspi_data";
> drive-strength = <8>;
> bias-pull-up;
> };
>
> - rclk-pins {
> - pins = "gpio10";
> - function = "sdc_rclk";
> - drive-strength = <8>;
> - bias-pull-down;
> - };
> + };
> +};
> +
> +&qpic_bam {
> + status = "okay";
> +};
> +
> +&qpic_nand {
> + status = "okay";
status should come last
> + pinctrl-0 = <&qspi_nand_pins>;
> + pinctrl-names = "default";
> + spi_nand: spi_nand@0 {
no underscores in node names
missing newline between properties and subnodes
> + compatible = "spi-nand";
> + nand-ecc-engine = <&qpic_nand>;
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + spi-max-frequency = <8000000>;
> };
> };
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index b44acb1fac74..f9c21373f5e6 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -336,10 +336,38 @@ sdhc_1: mmc@7804000 {
> status = "disabled";
> };
>
> + qpic_bam: dma@7984000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x7984000 0x1c000>;
> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + status = "disabled";
> + };
You're modifying the SoC and board devicetrees in one go, this won't fly
> +
> + qpic_nand: spi@79b0000 {
> + compatible = "qcom,ipq9574-nand";
> + reg = <0x79b0000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
these two properties usually go below status, at the end
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>,
> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
Indentation here is messy
> + clock-names = "core", "aon", "io_macro";
one per line, please
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
ditto
> + dma-names = "tx", "rx", "cmd";
ditto
> + nand-ecc-engine = <&bch>;
> + status = "disabled";
> + };
> +
> bch: qpic_ecc {
> compatible = "qcom,ipq9574-ecc";
> status = "ok";
> - }
> + };
This means the previous dt patch would not compile
Konrad
next prev parent reply other threads:[~2023-10-31 15:27 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-31 12:03 [RFC PATCH 0/5] Add QPIC SPI NAND driver support Md Sadre Alam
2023-10-31 12:03 ` [RFC PATCH 1/5] mtd: nand: ecc-qcom: Add support for ECC Engine Driver Md Sadre Alam
2023-10-31 15:28 ` Miquel Raynal
2023-11-03 12:06 ` Md Sadre Alam
2023-11-03 12:08 ` Krzysztof Kozlowski
2023-11-03 12:11 ` Krzysztof Kozlowski
2023-10-31 17:11 ` Krzysztof Kozlowski
2023-11-03 12:24 ` Md Sadre Alam
2023-11-03 12:33 ` Dmitry Baryshkov
2023-11-03 13:23 ` Md Sadre Alam
2023-11-03 13:46 ` Miquel Raynal
2023-11-20 6:30 ` Md Sadre Alam
2023-11-03 13:54 ` Dmitry Baryshkov
2023-10-31 12:03 ` [RFC PATCH 2/5] arm64: dts: qcom: ipq9574: Add ecc engine support Md Sadre Alam
2023-10-31 15:23 ` Konrad Dybcio
2023-11-03 11:26 ` Md Sadre Alam
2023-10-31 17:12 ` Krzysztof Kozlowski
2023-11-03 12:09 ` Md Sadre Alam
2023-10-31 12:03 ` [RFC PATCH 3/5] mtd: nand: qpic_common: Add support for qpic common API Md Sadre Alam
2023-10-31 15:54 ` Miquel Raynal
2023-10-31 12:03 ` [RFC PATCH 4/5] spi: qpic: Add support for qpic spi nand driver Md Sadre Alam
2023-10-31 14:23 ` Mark Brown
2023-11-03 11:20 ` Md Sadre Alam
2023-11-03 12:47 ` Mark Brown
2023-11-20 6:34 ` Md Sadre Alam
2023-10-31 17:13 ` Krzysztof Kozlowski
2023-11-03 12:13 ` Md Sadre Alam
2023-11-03 12:18 ` Krzysztof Kozlowski
2023-11-03 12:15 ` Md Sadre Alam
2023-10-31 12:03 ` [RFC PATCH 5/5] arm64: dts: qcom: ipq9574: Add support for SPI nand Md Sadre Alam
2023-10-31 15:27 ` Konrad Dybcio [this message]
2023-11-03 11:31 ` Md Sadre Alam
2023-10-31 17:17 ` Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8be3b4f4-f3d1-41c8-bd4a-90adf1a02ea6@linaro.org \
--to=konrad.dybcio@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=miquel.raynal@bootlin.com \
--cc=qpic_varada@quicinc.com \
--cc=quic_mdalam@quicinc.com \
--cc=quic_srichara@quicinc.com \
--cc=richard@nod.at \
--cc=robh+dt@kernel.org \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).