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([2600:8803:e7e4:500:c69c:7b5c:ce9b:24be]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7ce478af813sm5732105a34.19.2026.01.08.07.57.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Jan 2026 07:57:29 -0800 (PST) Message-ID: <97096aa2-acf1-4e4b-b03b-b538c3c1cf27@baylibre.com> Date: Thu, 8 Jan 2026 09:57:29 -0600 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/9] spi: Documentation: add page on multi-lane support To: Marcelo Schmitt Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> <20251219-spi-add-multi-bus-support-v4-5-145dc5204cd8@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/8/26 6:40 AM, Marcelo Schmitt wrote: > Hi David, > > Thanks for adding a doc for the multi-lane stuff. > Two minor comments inline. > > Reviewed-by: Marcelo Schmitt > > On 12/19, David Lechner wrote: >> Add a new page to Documentation/spi/ describing how multi-lane SPI >> support works. This is uncommon functionality so it deserves its own >> documentation page. >> >> Signed-off-by: David Lechner >> --- >> v4 changes: >> * New patch in v4. >> --- >> Documentation/spi/index.rst | 1 + >> Documentation/spi/multiple-data-lanes.rst | 217 ++++++++++++++++++++++++++++++ >> 2 files changed, 218 insertions(+) >> >> diff --git a/Documentation/spi/index.rst b/Documentation/spi/index.rst >> index 824ce42ed4f0..2c89b1ee39e2 100644 >> --- a/Documentation/spi/index.rst >> +++ b/Documentation/spi/index.rst >> @@ -9,6 +9,7 @@ Serial Peripheral Interface (SPI) >> >> spi-summary >> spidev >> + multiple-data-lanes >> butterfly >> spi-lm70llp >> spi-sc18is602 >> diff --git a/Documentation/spi/multiple-data-lanes.rst b/Documentation/spi/multiple-data-lanes.rst >> new file mode 100644 >> index 000000000000..b267f31f0bc8 >> --- /dev/null >> +++ b/Documentation/spi/multiple-data-lanes.rst >> @@ -0,0 +1,217 @@ >> +==================================== >> +SPI devices with multiple data lanes >> +==================================== >> + >> +Some specialized SPI controllers and peripherals support multiple data lanes >> +that allow reading more than one word at a time in parallel. This is different >> +from dual/quad/octal SPI where multiple bits of a single word are transferred >> +simultaneously. >> + >> +For example, controllers that support parallel flash memories have this feature >> +as do some simultaneous-sampling ADCs where each channel has its own data lane. >> + >> +--------------------- >> +Describing the wiring >> +--------------------- >> + >> +The ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the devicetree >> +are used to describe how many data lanes are connected between the controller >> +and how wide each lane is. The number of items in the array indicates how many >> +lanes there are, and the value of each item indicates how many bits wide that >> +lane is. >> + >> +For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be >> +wired up like this:: > At first, I thought calling these '4-bit lanes' was a bit confusing. I was > thinking about suggesting '4-wire lanes' but I guess 4-bit is more generic in > case we ever see a setup where data navigates through something besides wires. > >> + >> + +--------------+ +----------+ >> + | SPI | | AD4630 | >> + | Controller | | ADC | >> + | | | | >> + | CS0 |--->| CS | >> + | SCK |--->| SCK | >> + | SDO |--->| SDI | >> + | | | | >> + | SDIA0 |<---| SDOA0 | >> + | SDIA1 |<---| SDOA1 | >> + | SDIA2 |<---| SDOA2 | >> + | SDIA3 |<---| SDOA3 | >> + | | | | >> + | SDIB0 |<---| SDOB0 | >> + | SDIB1 |<---| SDOB1 | >> + | SDIB2 |<---| SDOB2 | >> + | SDIB3 |<---| SDOB3 | >> + | | | | >> + +--------------+ +----------+ >> + >> +It is described in a devicetree like this:: >> + >> + spi { >> + compatible = "my,spi-controller"; >> + >> + ... >> + >> + adc@0 { >> + compatible = "adi,ad4630"; >> + reg = <0>; >> + ... >> + spi-rx-bus-width = <4>, <4>; /* 2 lanes of 4 bits each */ >> + ... >> + }; >> + }; >> + >> +In most cases, lanes will be wired up symmetrically (A to A, B to B, etc). If >> +this isn't the case, extra ``spi-rx-bus-width`` and ``spi-tx-bus-width`` >> +properties are needed to provide a mapping between controller lanes and the >> +physical lane wires. >> + >> +Here is an example where a multi-lane SPI controller has each lane wired to >> +separate single-lane peripherals:: >> + >> + +--------------+ +----------+ >> + | SPI | | Thing 1 | >> + | Controller | | | >> + | | | | >> + | CS0 |--->| CS | >> + | SDO0 |--->| SDI | >> + | SDI0 |<---| SDO | >> + | SCLK0 |--->| SCLK | >> + | | | | >> + | | +----------+ >> + | | >> + | | +----------+ >> + | | | Thing 2 | >> + | | | | >> + | CS1 |--->| CS | >> + | SDO1 |--->| SDI | >> + | SDI1 |<---| SDO | >> + | SCLK1 |--->| SCLK | >> + | | | | >> + +--------------+ +----------+ >> + >> +This is described in a devicetree like this:: >> + >> + spi { >> + compatible = "my,spi-controller"; >> + >> + ... >> + >> + thing1@0 { >> + compatible = "my,thing1"; >> + reg = <0>; >> + ... >> + }; >> + >> + thing2@1 { >> + compatible = "my,thing2"; >> + reg = <1>; >> + ... >> + spi-tx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for tx wire */ >> + spi-rx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for rx wire */ > In this example, even though lane 0 is not used by thing2, it is being used by > thing1, right? Yes, I can improve the comments to make it more clear. > Just checking I understand it correctly. > >> + ... >> + }; >> + }; >> +