From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [QUERY] Behavior of spi slave memories w.r.t chip select signal. Date: Fri, 13 May 2011 08:54:03 +0200 Message-ID: References: <4DCA0B77.8060700@st.com> <4DCCAB19.2020302@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Dinesh Kumar SHARMA , martin.bergstrom-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org, Armando VISCONTI , Marcus COOPER , Shiraz HASHIM , Jamie Iles , spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, Vikas MANOCHA , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" To: viresh kumar Return-path: In-Reply-To: <4DCCAB19.2020302-qxv4g6HH51o@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org 2011/5/13 viresh kumar : > On 05/11/2011 09:37 AM, viresh kumar wrote: >> >> Hello, >> >> Following is what i understood after reading m25p80 driver and spi master >> drivers in drivers/spi folder. >> >> "chip_select signal controls start and end of transfer. For ex: if we have to read >> status reg of spi memory, then we use write_and_then_read() routine. which writes >> 0x9F in one spi transfer and writes dummy bytes and reads rx reg in other transfer. >> And these two transfers are part of single spi_message. >> >> Now, it is controllable to handle cs, and if we send cs_change == 0, then chip select >> is activated at start of message and deactivated at end of message, instead at end >> of every transfer. >> >> Which means, even if there is a delay between command and dummy bytes received at >> spi memory, current transfer will not be terminated by memory as cs is low." >> >> Is this correct?? >> >> Actually i am seeing a different behavior by some of the spi memories, like m25p10. >> If there is a delay between read_sts_reg command and dummy bytes, then 0xFFFFFF is >> returned in response. If there is no delay then transfer always passes. >> > > Linus, Jamie, > > Have you ever seen this kind of issue? Which spi slave memories did you used for testing? > I am using standard pl0022 and m25p80 driver. Tried in all modes: polling, interrupt, dma. Not really. I'll throw in a few people on CC and see if they have some hints. Linus Walleij ------------------------------------------------------------------------------ Achieve unprecedented app performance and reliability What every C/C++ and Fortran developer should know. Learn how Intel has extended the reach of its next-generation tools to help boost performance applications - inlcuding clusters. http://p.sf.net/sfu/intel-dev2devmay