From mboxrd@z Thu Jan  1 00:00:00 1970
From: padma venkat <padma.kvr@gmail.com>
Subject: Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level
Date: Fri, 1 Jul 2011 11:29:02 +0530
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Cc: Tony Nadackal <tonykn@gmail.com>,
	Padmavathi Venna <padma.v@samsung.com>, kgene.kim@samsung.com,
	sbkim73@samsung.com, grant.likely@secretlab.ca,
	spi-devel-general@lists.sourceforge.net,
	linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, tony.kn@samsung.com,
	naushad@samsung.com
To: Jassi Brar <jassisinghbrar@gmail.com>
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Hi Jassi,

On Fri, Jul 1, 2011 at 11:22 AM, Jassi Brar <jassisinghbrar@gmail.com> =
wrote:
> On Fri, Jul 1, 2011 at 11:16 AM, padma venkat <padma.kvr@gmail.com> w=
rote:
>> Hi Tony,
>>
>> On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal <tonykn@gmail.com> wr=
ote:
>>> Hi Padma,
>>> With regards to your patch, even though one can check the tx done s=
tatus
>>> using the TX_DONE bit, the present macro itself would work perfectl=
y fine if
>>> the 'fifo_lvl_mask' is set properly.
>>> For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff (f=
or 9bits,
>>> 15:23), while even in your patch, it is wrongly set as 0x7f(only 7b=
its).
>>>
>>> Thus, if this fifo_lvl_mask was defined correctly, the existing mac=
ro would
>>> itself have worked.
>> Thanks for your comment.
>> I considered changing to the fifo_lvl_mask to 1ff as you mentioned.
>> But I =A0think that the fifo_lvl_mask reflects the actual FIFO capac=
ity
>> in the SPI driver.
>> For the failing channels the FIFO trigger level is 64 bytes and so i
>> retained that value.
>> In the driver it polls till the FIFO capacity level otherwise it goe=
s
>> for DMA.So if we keep
>> the FIFO level as 1ff when the actual capacity is 7f then it fails.
>>
>> Jassi what do you think about this?
>>
>
> 'fifo_lvl_mask' is h/w specific and can't be set for convenience.
>
> I don't have access to post-s3c64xx datasheets.
> Please check and reply if TX_DONE bit is at same offset for all
> channels of an SoC, because
> I suspect it's otherwise.
>
Yes. The TX_DONE bit is at the same offset for all the channels of an S=
oC.
in S5P64X0,S5PV210 and S5PV310 it is at offset 25.