From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jassi Brar Subject: Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level Date: Fri, 1 Jul 2011 11:43:08 +0530 Message-ID: References: <1309437536-9315-1-git-send-email-padma.v@samsung.com> <1309437536-9315-2-git-send-email-padma.v@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Tony Nadackal , Padmavathi Venna , kgene.kim@samsung.com, sbkim73@samsung.com, grant.likely@secretlab.ca, spi-devel-general@lists.sourceforge.net, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tony.kn@samsung.com, naushad@samsung.com To: padma venkat Return-path: In-Reply-To: Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-spi.vger.kernel.org On Fri, Jul 1, 2011 at 11:29 AM, padma venkat wro= te: > Hi Jassi, > > On Fri, Jul 1, 2011 at 11:22 AM, Jassi Brar wrote: >> On Fri, Jul 1, 2011 at 11:16 AM, padma venkat = wrote: >>> Hi Tony, >>> >>> On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal w= rote: >>>> Hi Padma, >>>> With regards to your patch, even though one can check the tx done = status >>>> using the TX_DONE bit, the present macro itself would work perfect= ly fine if >>>> the 'fifo_lvl_mask' is set properly. >>>> For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff (= for 9bits, >>>> 15:23), while even in your patch, it is wrongly set as 0x7f(only 7= bits). >>>> >>>> Thus, if this fifo_lvl_mask was defined correctly, the existing ma= cro would >>>> itself have worked. >>> Thanks for your comment. >>> I considered changing to the fifo_lvl_mask to 1ff as you mentioned. >>> But I =C2=A0think that the fifo_lvl_mask reflects the actual FIFO c= apacity >>> in the SPI driver. >>> For the failing channels the FIFO trigger level is 64 bytes and so = i >>> retained that value. >>> In the driver it polls till the FIFO capacity level otherwise it go= es >>> for DMA.So if we keep >>> the FIFO level as 1ff when the actual capacity is 7f then it fails. >>> >>> Jassi what do you think about this? >>> >> >> 'fifo_lvl_mask' is h/w specific and can't be set for convenience. >> >> I don't have access to post-s3c64xx datasheets. >> Please check and reply if TX_DONE bit is at same offset for all >> channels of an SoC, because >> I suspect it's otherwise. >> > Yes. The TX_DONE bit is at the same offset for all the channels of an= SoC. > in S5P64X0,S5PV210 and S5PV310 it is at offset 25. > Then, Patches-1,2 Acked-by: Jassi Brar