[PATCH 1/2] spi: cadence: Init HW after reading devicetree attributes

[PATCH 1/2] spi: cadence: Init HW after reading devicetree attributes

[Lars-Peter Clausen]

From: Paul Cercueil <paul.cercueil-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>

This will make it possible to use the settings specified in the devicetree
to configure the hardware.

Signed-off-by: Paul Cercueil <paul.cercueil-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
---
 drivers/spi/spi-cadence.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 7b811e3..2404937 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -516,6 +516,17 @@ static int cdns_spi_probe(struct platform_device *pdev)
 		goto clk_dis_apb;
 	}
 
+	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
+	if (ret < 0)
+		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
+	else
+		master->num_chipselect = num_cs;
+
+	ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
+				   &xspi->is_decoded_cs);
+	if (ret < 0)
+		xspi->is_decoded_cs = 0;
+
 	/* SPI controller initializations */
 	cdns_spi_init_hw(xspi);
 
@@ -534,19 +545,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
 		goto remove_master;
 	}
 
-	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
-
-	if (ret < 0)
-		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
-	else
-		master->num_chipselect = num_cs;
-
-	ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
-				   &xspi->is_decoded_cs);
-
-	if (ret < 0)
-		xspi->is_decoded_cs = 0;
-
 	master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 	master->prepare_message = cdns_prepare_message;
 	master->transfer_one = cdns_transfer_one;
-- 
1.8.0

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[PATCH 2/2] spi: cadence: Fix 3-to-8 mux mode

[Lars-Peter Clausen]

In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
control register. Currently the driver never sets this bit even when
configured for 3-to-8 mux mode. This patch adds code which sets the bit
during device initialization when necessary.

Signed-off-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
---
 drivers/spi/spi-cadence.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 2404937..5a67498 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -47,6 +47,7 @@
 #define CDNS_SPI_CR_CPHA_MASK		0x00000004 /* Clock Phase Control */
 #define CDNS_SPI_CR_CPOL_MASK		0x00000002 /* Clock Polarity Control */
 #define CDNS_SPI_CR_SSCTRL_MASK		0x00003C00 /* Slave Select Mask */
+#define CDNS_SPI_CR_PERI_SEL_MASK	0x00000200 /* Peripheral Select Decode */
 #define CDNS_SPI_CR_BAUD_DIV_MASK	0x00000038 /* Baud Rate Divisor Mask */
 #define CDNS_SPI_CR_MSTREN_MASK		0x00000001 /* Master Enable Mask */
 #define CDNS_SPI_CR_MANSTRTEN_MASK	0x00008000 /* Manual TX Enable Mask */
@@ -148,6 +149,11 @@ static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
  */
 static void cdns_spi_init_hw(struct cdns_spi *xspi)
 {
+	u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;
+
+	if (xspi->is_decoded_cs)
+		ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;
+
 	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
 		       CDNS_SPI_ER_DISABLE_MASK);
 	cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
@@ -160,8 +166,7 @@ static void cdns_spi_init_hw(struct cdns_spi *xspi)
 
 	cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
 		       CDNS_SPI_IXR_ALL_MASK);
-	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET,
-		       CDNS_SPI_CR_DEFAULT_MASK);
+	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
 	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
 		       CDNS_SPI_ER_ENABLE_MASK);
 }
-- 
1.8.0

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Re: [PATCH 2/2] spi: cadence: Fix 3-to-8 mux mode

[Harini Katakam]

On Thu, Nov 27, 2014 at 8:42 PM, Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org> wrote:
> In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
> control register. Currently the driver never sets this bit even when
> configured for 3-to-8 mux mode. This patch adds code which sets the bit
> during device initialization when necessary.
>
> Signed-off-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>

Acked-by: Harini Katakam <harinik-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Regards,
Harini
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Re: [PATCH 1/2] spi: cadence: Init HW after reading devicetree attributes

[Michal Simek]

On 11/27/2014 04:12 PM, Lars-Peter Clausen wrote:
> From: Paul Cercueil <paul.cercueil-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
> 
> This will make it possible to use the settings specified in the devicetree
> to configure the hardware.
> 
> Signed-off-by: Paul Cercueil <paul.cercueil-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
> ---
>  drivers/spi/spi-cadence.c | 24 +++++++++++-------------
>  1 file changed, 11 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
> index 7b811e3..2404937 100644
> --- a/drivers/spi/spi-cadence.c
> +++ b/drivers/spi/spi-cadence.c
> @@ -516,6 +516,17 @@ static int cdns_spi_probe(struct platform_device *pdev)
>  		goto clk_dis_apb;
>  	}
>  
> +	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
> +	if (ret < 0)
> +		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
> +	else
> +		master->num_chipselect = num_cs;
> +
> +	ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
> +				   &xspi->is_decoded_cs);
> +	if (ret < 0)
> +		xspi->is_decoded_cs = 0;
> +
>  	/* SPI controller initializations */
>  	cdns_spi_init_hw(xspi);
>  
> @@ -534,19 +545,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
>  		goto remove_master;
>  	}
>  
> -	ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
> -
> -	if (ret < 0)
> -		master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
> -	else
> -		master->num_chipselect = num_cs;
> -
> -	ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
> -				   &xspi->is_decoded_cs);
> -
> -	if (ret < 0)
> -		xspi->is_decoded_cs = 0;
> -
>  	master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
>  	master->prepare_message = cdns_prepare_message;
>  	master->transfer_one = cdns_transfer_one;
> 

That's reasonable patch to do without any functional impact now.

Reviewed-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Thanks,
Michal

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Re: [PATCH 1/2] spi: cadence: Init HW after reading devicetree attributes

[Mark Brown]

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On Thu, Nov 27, 2014 at 04:12:17PM +0100, Lars-Peter Clausen wrote:
> From: Paul Cercueil <paul.cercueil-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>
> 
> This will make it possible to use the settings specified in the devicetree
> to configure the hardware.

Applied both, thanks.

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