Re: [patch v9 0/4] JTAG driver introduction

Re: [patch v9 0/4] JTAG driver introduction

[Geert Uytterhoeven]

Hi Oleksandr,

[My attention was drawn by https://lwn.net/Articles/734440/]
[CC linux-spi, which was never included, while linux-serial was]

On Thu, Sep 21, 2017 at 11:25 AM, Oleksandr Shamray
<oleksandrs-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org> wrote:
> When a need raise up to use JTAG interface for system's devices
> programming or CPU debugging, usually the user layer
> application implements jtag protocol by bit-bang or using a
> proprietary connection to vendor hardware.
> This method can be slow and not generic.
>
> We propose to implement general JTAG interface and infrastructure
> to communicate with user layer application. In such way, we can
> have the standard JTAG interface core part and separation from
> specific HW implementation.
> This allow new capability to debug the CPU or program system's
> device via BMC without additional devices nor cost.
>
> This patch purpose is to add JTAG master core infrastructure by
> defining new JTAG class and provide generic JTAG interface
> to allow hardware specific drivers to connect this interface.
> This will enable all JTAG drivers to use the common interface
> part and will have separate for hardware implementation.
>
> The JTAG (Joint Test Action Group) core driver provides minimal generic
> JTAG interface, which can be used by hardware specific JTAG master
> controllers. By providing common interface for the JTAG controllers,
> user space device programing is hardware independent.
>
> Modern SoC which in use for embedded system' equipped with
> internal JTAG master interface.
> This interface is used for programming and debugging system's
> hardware components, like CPLD, FPGA, CPU, voltage and
> industrial controllers.
> Firmware for such devices can be upgraded through JTAG interface during
> Runtime. The JTAG standard support for multiple devices programming,
> is in case their lines are daisy-chained together.
>
> For example, systems which equipped with host CPU, BMC SoC or/and
> number of programmable devices are capable to connect a pin and
> select system components dynamically for programming and debugging,
> This is using by the BMC which is equipped with internal SoC master
> controller.
> For example:
>
> BMC JTAG master --> pin selected to CPLDs chain for programming (filed
> upgrade, production)
> BMC JTAG master --> pin selected to voltage monitors for programming
> (field upgrade, production)
> BMC JTAG master --> pin selected to host CPU (on-site debugging
> and developers debugging)
>
> For example, we can have application in user space which using calls
> to JTAG driver executes CPLD programming directly from SVF file
>
> The JTAG standard (IEEE 1149.1) defines the next connector pins:
> - TDI (Test Data In);
> - TDO (Test Data Out);
> - TCK (Test Clock);
> - TMS (Test Mode Select);
> - TRST (Test Reset) (Optional);
>
> The SoC equipped with JTAG master controller, performs
> device programming on command or vector level. For example
> a file in a standard SVF (Serial Vector Format) that contains
> boundary scan vectors, can be used by sending each vector
> to the JTAG interface and the JTAG controller will execute
> the programming.
>
> Initial version provides the system calls set for:
> - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
> - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
> - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
>   number of clocks.
>
> SoC which are not equipped with JTAG master interface, can be built
> on top of JTAG core driver infrastructure, by applying bit-banging of
> TDI, TDO, TCK and TMS pins within the hardware specific driver.

Or by using an SPI master?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [patch v9 0/4] JTAG driver introduction

[Oleksandr Shamray]

> -----Original Message-----
> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com]
> On Behalf Of Geert Uytterhoeven
> Sent: Thursday, September 28, 2017 11:33 AM
> To: Oleksandr Shamray <oleksandrs@mellanox.com>
> Cc: Greg KH <gregkh@linuxfoundation.org>; Arnd Bergmann
> <arnd@arndb.de>; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org;
> openbmc@lists.ozlabs.org; Joel Stanley <joel@jms.id.au>; Jiri Pirko
> <jiri@resnulli.us>; Tobias Klauser <tklauser@distanz.ch>; linux-
> serial@vger.kernel.org; mec@shout.net; Vadim Pasternak
> <vadimp@mellanox.com>; system-sw-low-level <system-sw-low-
> level@mellanox.com>; Rob Herring <robh+dt@kernel.org>; openocd-devel-
> owner@lists.sourceforge.net; linux-api@vger.kernel.org; David S. Miller
> <davem@davemloft.net>; Mauro Carvalho Chehab <mchehab@kernel.org>;
> linux-spi <linux-spi@vger.kernel.org>; Mark Brown <broonie@kernel.org>
> Subject: Re: [patch v9 0/4] JTAG driver introduction
> 
> Hi Oleksandr,
> 
> [My attention was drawn by
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flwn.net
> %2FArticles%2F734440%2F&data=02%7C01%7Coleksandrs%40mellanox.com%7
> C97b8ba88686a42daaace08d5064b92eb%7Ca652971c7d2e4d9ba6a4d149256f
> 461b%7C0%7C0%7C636421844026854216&sdata=TeHD4a3%2FBN6a5XG3Jizf5
> pmsyJHJjzkEzkpnqsXC6S0%3D&reserved=0]
> [CC linux-spi, which was never included, while linux-serial was]
> 
> On Thu, Sep 21, 2017 at 11:25 AM, Oleksandr Shamray
> <oleksandrs@mellanox.com> wrote:
> > When a need raise up to use JTAG interface for system's devices
> > programming or CPU debugging, usually the user layer application
> > implements jtag protocol by bit-bang or using a proprietary connection
> > to vendor hardware.
> > This method can be slow and not generic.
> >


[..]

> >
> > Initial version provides the system calls set for:
> > - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
> > - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
> > - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
> >   number of clocks.
> >
> > SoC which are not equipped with JTAG master interface, can be built on
> > top of JTAG core driver infrastructure, by applying bit-banging of
> > TDI, TDO, TCK and TMS pins within the hardware specific driver.
> 
> Or by using an SPI master?
> 

I think it depends on how flexible the SPI interface is. If you can set it to transfer 
from 1 to n bits at a time, and you control the TMS line in software, you should 
be able to use it. If the SPI interface can only transfer a multiple of 8 bits 
at a time, then in general it would not be suitable for JTAG.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [patch v9 0/4] JTAG driver introduction

[Geert Uytterhoeven]

Hi Oleksandr,

On Thu, Sep 28, 2017 at 10:53 AM, Oleksandr Shamray
<oleksandrs@mellanox.com> wrote:
>> [My attention was drawn by
>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flwn.net
>> %2FArticles%2F734440%2F&data=02%7C01%7Coleksandrs%40mellanox.com%7
>> C97b8ba88686a42daaace08d5064b92eb%7Ca652971c7d2e4d9ba6a4d149256f
>> 461b%7C0%7C0%7C636421844026854216&sdata=TeHD4a3%2FBN6a5XG3Jizf5
>> pmsyJHJjzkEzkpnqsXC6S0%3D&reserved=0]
>> [CC linux-spi, which was never included, while linux-serial was]
>>
>> On Thu, Sep 21, 2017 at 11:25 AM, Oleksandr Shamray
>> <oleksandrs@mellanox.com> wrote:
>> > When a need raise up to use JTAG interface for system's devices
>> > programming or CPU debugging, usually the user layer application
>> > implements jtag protocol by bit-bang or using a proprietary connection
>> > to vendor hardware.
>> > This method can be slow and not generic.
>> >
>
>
> [..]
>
>> >
>> > Initial version provides the system calls set for:
>> > - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
>> > - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
>> > - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
>> >   number of clocks.
>> >
>> > SoC which are not equipped with JTAG master interface, can be built on
>> > top of JTAG core driver infrastructure, by applying bit-banging of
>> > TDI, TDO, TCK and TMS pins within the hardware specific driver.
>>
>> Or by using an SPI master?
>>
>
> I think it depends on how flexible the SPI interface is. If you can set it to transfer
> from 1 to n bits at a time, and you control the TMS line in software, you should
> be able to use it. If the SPI interface can only transfer a multiple of 8 bits
> at a time, then in general it would not be suitable for JTAG.

Sure, that depends on the actual SPI master interface.
But I guess you can write a generic JTAG-over-SPI driver, and use a tms-gpios
property in DT to specify how to control TMS.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [patch v9 0/4] JTAG driver introduction

[Oleksandr Shamray]

> -----Original Message-----
> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com]
> On Behalf Of Geert Uytterhoeven
> Sent: Thursday, September 28, 2017 12:02 PM
> To: Oleksandr Shamray <oleksandrs@mellanox.com>
> Cc: Greg KH <gregkh@linuxfoundation.org>; Arnd Bergmann
> <arnd@arndb.de>; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org;
> openbmc@lists.ozlabs.org; Joel Stanley <joel@jms.id.au>; Jiri Pirko
> <jiri@resnulli.us>; Tobias Klauser <tklauser@distanz.ch>; linux-
> serial@vger.kernel.org; mec@shout.net; Vadim Pasternak
> <vadimp@mellanox.com>; system-sw-low-level <system-sw-low-
> level@mellanox.com>; Rob Herring <robh+dt@kernel.org>; openocd-devel-
> owner@lists.sourceforge.net; linux-api@vger.kernel.org; David S. Miller
> <davem@davemloft.net>; Mauro Carvalho Chehab <mchehab@kernel.org>;
> linux-spi <linux-spi@vger.kernel.org>; Mark Brown <broonie@kernel.org>
> Subject: Re: [patch v9 0/4] JTAG driver introduction
> 
> Hi Oleksandr,
> 
> On Thu, Sep 28, 2017 at 10:53 AM, Oleksandr Shamray
> <oleksandrs@mellanox.com> wrote:
> >> [My attention was drawn by
> >> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flw
> >> n.net
> >>
> %2FArticles%2F734440%2F&data=02%7C01%7Coleksandrs%40mellanox.com%7
> >>
> C97b8ba88686a42daaace08d5064b92eb%7Ca652971c7d2e4d9ba6a4d149256f
> >>
> 461b%7C0%7C0%7C636421844026854216&sdata=TeHD4a3%2FBN6a5XG3Jizf5
> >> pmsyJHJjzkEzkpnqsXC6S0%3D&reserved=0]
> >> [CC linux-spi, which was never included, while linux-serial was]
> >>
> >> On Thu, Sep 21, 2017 at 11:25 AM, Oleksandr Shamray
> >> <oleksandrs@mellanox.com> wrote:
> >> > When a need raise up to use JTAG interface for system's devices
> >> > programming or CPU debugging, usually the user layer application
> >> > implements jtag protocol by bit-bang or using a proprietary
> >> > connection to vendor hardware.
> >> > This method can be slow and not generic.
> >> >
> >
> >
> > [..]
> >
> >> >
> >> > Initial version provides the system calls set for:
> >> > - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
> >> > - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
> >> > - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
> >> >   number of clocks.
> >> >
> >> > SoC which are not equipped with JTAG master interface, can be built
> >> > on top of JTAG core driver infrastructure, by applying bit-banging
> >> > of TDI, TDO, TCK and TMS pins within the hardware specific driver.
> >>
> >> Or by using an SPI master?
> >>
> >
> > I think it depends on how flexible the SPI interface is. If you can
> > set it to transfer from 1 to n bits at a time, and you control the TMS
> > line in software, you should be able to use it. If the SPI interface
> > can only transfer a multiple of 8 bits at a time, then in general it would not be
> suitable for JTAG.
> 
> Sure, that depends on the actual SPI master interface.
> But I guess you can write a generic JTAG-over-SPI driver, and use a tms-gpios
> property in DT to specify how to control TMS.
> 

Yes, this is a good idea for SoC which are not equipped with JTAG hardware.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds