[PATCH] spi: s3c64xx: do not disable the clock while configuring the spi

[PATCH] spi: s3c64xx: do not disable the clock while configuring the spi

[Andi Shyti]

When the clock is coming from the cmu it is not required to be
disabled and then re-enabled in order to change the rate.

Besides, some exynos chipsets (e.g. exynos5433) do not deliver
any to the SFR if one from the pclk ("spi" in this case) or sclk
("busclk") is disabled.

Remove the clock disabling/enabling to avoid falling into this
situation.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
---

Hi,

This patch has been tested by me and Sylwester on Trats2
(exynos4412) and tm2(e) (exynos5433) boards, for big data
(which use dma transfer) and small data.

It also fixes in exynos5433 a synchronus abort caused by the fact
that the pclk (spi) doesn't get delivered if the sclk is disabled
(busclk)

Thanks,
Andi

 drivers/spi/spi-s3c64xx.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 048c900..c719e73 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -577,9 +577,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 	u32 val;
 
 	/* Disable Clock */
-	if (sdd->port_conf->clk_from_cmu) {
-		clk_disable_unprepare(sdd->src_clk);
-	} else {
+	if (!sdd->port_conf->clk_from_cmu) {
 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
 		val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 		writel(val, regs + S3C64XX_SPI_CLK_CFG);
@@ -622,11 +620,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
 	if (sdd->port_conf->clk_from_cmu) {
-		/* Configure Clock */
-		/* There is half-multiplier before the SPI */
 		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
-		/* Enable Clock */
-		clk_prepare_enable(sdd->src_clk);
 	} else {
 		/* Configure Clock */
 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
-- 
2.8.1

Re: [PATCH] spi: s3c64xx: do not disable the clock while configuring the spi

[Krzysztof Kozlowski]

On 07/07/2016 09:23 AM, Andi Shyti wrote:
> When the clock is coming from the cmu it is not required to be
> disabled and then re-enabled in order to change the rate.
> 
> Besides, some exynos chipsets (e.g. exynos5433) do not deliver
> any to the SFR if one from the pclk ("spi" in this case) or sclk
> ("busclk") is disabled.
> 
> Remove the clock disabling/enabling to avoid falling into this
> situation.
> 
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
> 
> Hi,
> 
> This patch has been tested by me and Sylwester on Trats2
> (exynos4412) and tm2(e) (exynos5433) boards, for big data
> (which use dma transfer) and small data.
> 
> It also fixes in exynos5433 a synchronus abort caused by the fact
> that the pclk (spi) doesn't get delivered if the sclk is disabled
> (busclk)
> 
> Thanks,
> Andi
> 
>  drivers/spi/spi-s3c64xx.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

Re: [PATCH] spi: s3c64xx: do not disable the clock while configuring the spi

[Andi Shyti]

Hi,

>  	if (sdd->port_conf->clk_from_cmu) {
> -		/* Configure Clock */
> -		/* There is half-multiplier before the SPI */
>  		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);

sorry, I will re-send it because I should not remove the comments
above.... in the future someone might wonder why it's multiplied
by 2.

That's called auto review and auto-nack :)

Andi

> -		/* Enable Clock */
> -		clk_prepare_enable(sdd->src_clk);
>  	} else {
>  		/* Configure Clock */
>  		val = readl(regs + S3C64XX_SPI_CLK_CFG);
> -- 
> 2.8.1
> 

Re: [PATCH] spi: s3c64xx: do not disable the clock while configuring the spi

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 302 bytes --]

On Thu, Jul 07, 2016 at 06:58:41PM +0900, Andi Shyti wrote:

> sorry, I will re-send it because I should not remove the comments
> above.... in the future someone might wonder why it's multiplied
> by 2.

I already applied and published this, can you please send an incremental
patch fixing the issue?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

Applied "spi: s3c64xx: do not disable the clock while configuring the spi" to the spi tree

[Mark Brown]

The patch

   spi: s3c64xx: do not disable the clock while configuring the spi

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From d9aaf1dc984a448ae5630e53a611a8b3489d1f8d Mon Sep 17 00:00:00 2001
From: Andi Shyti <andi.shyti@samsung.com>
Date: Thu, 7 Jul 2016 16:23:57 +0900
Subject: [PATCH] spi: s3c64xx: do not disable the clock while configuring the
 spi

When the clock is coming from the cmu it is not required to be
disabled and then re-enabled in order to change the rate.

Besides, some exynos chipsets (e.g. exynos5433) do not deliver
any to the SFR if one from the pclk ("spi" in this case) or sclk
("busclk") is disabled.

Remove the clock disabling/enabling to avoid falling into this
situation.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-s3c64xx.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 9f0119f64f93..df88fa161d8a 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -596,9 +596,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 	u32 val;
 
 	/* Disable Clock */
-	if (sdd->port_conf->clk_from_cmu) {
-		clk_disable_unprepare(sdd->src_clk);
-	} else {
+	if (!sdd->port_conf->clk_from_cmu) {
 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
 		val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 		writel(val, regs + S3C64XX_SPI_CLK_CFG);
@@ -641,11 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
 	if (sdd->port_conf->clk_from_cmu) {
-		/* Configure Clock */
-		/* There is half-multiplier before the SPI */
 		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
-		/* Enable Clock */
-		clk_prepare_enable(sdd->src_clk);
 	} else {
 		/* Configure Clock */
 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
-- 
2.8.1