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controller driver To: Longbin Li Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou References: <20250224101213.26003-1-looong.bin@gmail.com> <20250224101213.26003-3-looong.bin@gmail.com> From: Chen Wang In-Reply-To: <20250224101213.26003-3-looong.bin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TYCP286CA0128.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b6::18) To PN0PR01MB9166.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:165::9) X-Microsoft-Original-Message-ID: <7a40a805-5afe-4f7d-bf74-44e975e256af@outlook.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email 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X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA1PR01MB4370 As I mention in anther comment, please use "SG2044" instead of "Sophgo" On 2025/2/24 18:12, Longbin Li wrote: > Add support for Sophgo SPI NOR controller in Sophgo SoC. s/Sophgo/SG2044 > > Signed-off-by: Longbin Li > --- > drivers/spi/Kconfig | 9 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-sophgo-nor.c | 501 +++++++++++++++++++++++++++++++++++ spi-sophgo-nor.c -> spi-sg2044-nor.c > 3 files changed, 511 insertions(+) > create mode 100644 drivers/spi/spi-sophgo-nor.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index ea8a31032927..6b6d7b348485 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -1021,6 +1021,15 @@ config SPI_SN_F_OSPI > for connecting an SPI Flash memory over up to 8-bit wide bus. > It supports indirect access mode only. > > +config SPI_SOPHGO_NOR SPI_SOPHGO_NOR -> SPI_SG2044_NOR > + tristate "Sophgo SPI NOR Controller" > + depends on ARCH_SOPHGO || COMPILE_TEST > + help > + This enables support for the Sophgo SPI NOR controller, > + which supports Dual/Qual read and write operations while > + also supporting 3Byte address devices and 4Byte address > + devices. > + > config SPI_SPRD > tristate "Spreadtrum SPI controller" > depends on ARCH_SPRD || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 9db7554c1864..9ded1de4b2fd 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -134,6 +134,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o > obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o > obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o > obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o > +obj-$(CONFIG_SPI_SOPHGO_NOR) += spi-sophgo-nor.o > obj-$(CONFIG_SPI_SPRD) += spi-sprd.o > obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o > obj-$(CONFIG_SPI_STM32) += spi-stm32.o > diff --git a/drivers/spi/spi-sophgo-nor.c b/drivers/spi/spi-sophgo-nor.c > new file mode 100644 > index 000000000000..1139deeac327 > --- /dev/null > +++ b/drivers/spi/spi-sophgo-nor.c > @@ -0,0 +1,501 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Sophgo SPI NOR controller driver > + * > + * Copyright (c) 2025 Longbin Li > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* Hardware register definitions */ > +#define SPIFMC_CTRL 0x00 > +#define SPIFMC_CTRL_CPHA BIT(12) > +#define SPIFMC_CTRL_CPOL BIT(13) > +#define SPIFMC_CTRL_HOLD_OL BIT(14) > +#define SPIFMC_CTRL_WP_OL BIT(15) > +#define SPIFMC_CTRL_LSBF BIT(20) > +#define SPIFMC_CTRL_SRST BIT(21) > +#define SPIFMC_CTRL_SCK_DIV_SHIFT 0 > +#define SPIFMC_CTRL_FRAME_LEN_SHIFT 16 > +#define SPIFMC_CTRL_SCK_DIV_MASK 0x7FF > + > +#define SPIFMC_CE_CTRL 0x04 > +#define SPIFMC_CE_CTRL_CEMANUAL BIT(0) > +#define SPIFMC_CE_CTRL_CEMANUAL_EN BIT(1) > + > +#define SPIFMC_DLY_CTRL 0x08 > +#define SPIFMC_CTRL_FM_INTVL_MASK 0x000f > +#define SPIFMC_CTRL_FM_INTVL BIT(0) > +#define SPIFMC_CTRL_CET_MASK 0x0f00 > +#define SPIFMC_CTRL_CET BIT(8) > + > +#define SPIFMC_DMMR 0x0c > + > +#define SPIFMC_TRAN_CSR 0x10 > +#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK GENMASK(1, 0) > +#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0) > +#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1) > +#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3) > +#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4) > +#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4) > +#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4) > +#define SPIFMC_TRAN_CSR_DMA_EN BIT(6) > +#define SPIFMC_TRAN_CSR_MISO_LEVEL BIT(7) > +#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK GENMASK(10, 8) > +#define SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT 8 > +#define SPIFMC_TRAN_CSR_WITH_CMD BIT(11) > +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK GENMASK(13, 12) > +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE (0x00 << 12) > +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_2_BYTE (0x01 << 12) > +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE (0x02 << 12) > +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE (0x03 << 12) > +#define SPIFMC_TRAN_CSR_GO_BUSY BIT(15) > +#define SPIFMC_TRAN_CSR_ADDR4B_SHIFT 20 > +#define SPIFMC_TRAN_CSR_CMD4B_SHIFT 21 > + > +#define SPIFMC_TRAN_NUM 0x14 > +#define SPIFMC_FIFO_PORT 0x18 > +#define SPIFMC_FIFO_PT 0x20 > + > +#define SPIFMC_INT_STS 0x28 > +#define SPIFMC_INT_TRAN_DONE BIT(0) > +#define SPIFMC_INT_RD_FIFO BIT(2) > +#define SPIFMC_INT_WR_FIFO BIT(3) > +#define SPIFMC_INT_RX_FRAME BIT(4) > +#define SPIFMC_INT_TX_FRAME BIT(5) > + > +#define SPIFMC_INT_EN 0x2c > +#define SPIFMC_INT_TRAN_DONE_EN BIT(0) > +#define SPIFMC_INT_RD_FIFO_EN BIT(2) > +#define SPIFMC_INT_WR_FIFO_EN BIT(3) > +#define SPIFMC_INT_RX_FRAME_EN BIT(4) > +#define SPIFMC_INT_TX_FRAME_EN BIT(5) > + > +#define SPIFMC_OPT 0x030 > +#define SPIFMC_OPT_DISABLE_FIFO_FLUSH BIT(1) > + > +#define SPIFMC_MAX_FIFO_DEPTH 8 > + > +#define SPIFMC_MAX_READ_SIZE 0x10000 > + > +struct sophgo_spifmc { > + struct spi_controller *ctrl; > + void __iomem *io_base; > + struct device *dev; > + struct mutex lock; > + struct clk *clk; > +}; "sophgo_" -> "sg2044_", for structure and function names, ... [......] > + > +MODULE_DESCRIPTION("Sophgo SPI NOR controller driver"); Sophgo -> SG2044 > +MODULE_AUTHOR("Longbin Li "); > +MODULE_LICENSE("GPL"); > -- > 2.48.1