Re: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling

[Mark Brown <broonie@kernel.org>]

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On Thu, Feb 23, 2023 at 09:56:35PM +0530, Krishna Yarlagadda wrote:

> Trusted Platform Module requires flow control. As defined in TPM
> interface specification, client would drive MISO line at same cycle as
> last address bit on MOSI.
> Tegra241 QSPI controller has TPM wait state detection feature which is
> enabled for TPM client devices reported in SPI device mode bits.
> Set half duplex flag for TPM device to detect and send entire message
> to controller in one shot.

I don't really understand what the controller is actually doing here, or
what the intended effect of the SPI_TPM_HW_FLOW flag is supposed to be.

>  	/* Enable Combined sequence mode */
>  	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
> +	if (spi->mode & SPI_TPM_HW_FLOW) {
> +		if (tqspi->soc_data->tpm_wait_poll)
> +			val |= QSPI_TPM_WAIT_POLL_EN;
> +		else
> +			return -EIO;
> +	}

This just sets a bit in a register...

>  	val |= QSPI_CMB_SEQ_EN;
>  	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
>  	/* Process individual transfer list */

...my guess is that setting that bit causes the individual transfers to
be delayed in completing without further changes?  Is is just some
transfers or all of them?

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