[PATCH v6 0/3] Stacked/parallel memories bindings

[PATCH v6 0/3] Stacked/parallel memories bindings

[Miquel Raynal]

Hello Rob, Mark, Tudor & Pratyush,

Here is a sixth versions for these bindings, which applies on top of
the v5.17-rc1 now that Pratyush's work as been merged.
(https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/)

Cheers,
Miquèl

Changes in v6:
* Added Pratyush's acks.
* The tooling now validates the binding (updating dt-schema is
  necesary).
* Updated the maxItems field to 4 as a "big enough value" as discussed.

Changes in v5:
* Used the uint64-array instead of the matrix type.
* Updated the example as well to use a single "/bits/ 64" cast because
  doing it twice, despite being supported by the language itself, is not
  yet something that we can use for describing bindings.

Changes in v4:
* Changed the type of properties to uint64-arrays in order to be able to
  describe the size of each element in the array.
* Updated the example accordingly.

Changes in v3:
* Rebased on top of Pratyush's recent changes.
* Dropped the commit allowing to provide two reg entries on the node
  name.
* Dropped the commit referencing spi-controller.yaml from
  jedec,spi-nor.yaml, now replaced by spi-peripheral-props.yaml and
  already done in Pratyush's series.
* Added Rob's Ack.
* Enhanced a commit message.
* Moved the new properties to the new SPI peripheral binding file.

Changes in v2:
* Dropped the dtc changes for now.
* Moved the properties in the device's nodes, not the controller's.
* Dropped the useless #address-cells change.
* Added a missing "minItems".
* Moved the new properties in the spi-controller.yaml file.
* Added an example using two stacked memories in the
  spi-controller.yaml file.
* Renamed the properties to drop the Xilinx prefix.
* Added a patch to fix the spi-nor jedec yaml file.

Miquel Raynal (3):
  dt-bindings: mtd: spi-nor: Allow two CS per device
  spi: dt-bindings: Describe stacked/parallel memories modes
  spi: dt-bindings: Add an example with two stacked flashes

 .../bindings/mtd/jedec,spi-nor.yaml           |  3 ++-
 .../bindings/spi/spi-controller.yaml          |  7 ++++++
 .../bindings/spi/spi-peripheral-props.yaml    | 25 +++++++++++++++++++
 3 files changed, 34 insertions(+), 1 deletion(-)

-- 
2.27.0

[PATCH v6 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device

[Miquel Raynal]

The Xilinx QSPI controller has two advanced modes which allow the
controller to behave differently and consider two flashes as one single
storage.

One of these two modes is quite complex to support from a binding point
of view and is the dual parallel memories. In this mode, each byte of
data is stored in both devices: the even bits in one, the odd bits in
the other. The split is automatically handled by the QSPI controller and
is transparent for the user.

The other mode is simpler to support, it is called dual stacked
memories. The controller shares the same SPI bus but each of the devices
contain half of the data. Once in this mode, the controller does not
follow CS requests but instead internally wires the two CS levels with
the value of the most significant address bit.

Supporting these two modes will involve core changes which include the
possibility of providing two CS for a single SPI device

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 39421f7233e4..4abfb4cfc157 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -47,7 +47,8 @@ properties:
       identified by the JEDEC READ ID opcode (0x9F).
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   spi-max-frequency: true
   spi-rx-bus-width: true
-- 
2.27.0

[PATCH v6 2/3] spi: dt-bindings: Describe stacked/parallel memories modes

[Miquel Raynal]

Describe two new memories modes:
- A stacked mode when the bus is common but the address space extended
  with an additinals wires.
- A parallel mode with parallel busses accessing parallel flashes where
  the data is spread.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
 .../bindings/spi/spi-peripheral-props.yaml    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 5dd209206e88..fedb7ae98ff6 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -82,6 +82,31 @@ properties:
     description:
       Delay, in microseconds, after a write transfer.
 
+  stacked-memories:
+    description: Several SPI memories can be wired in stacked mode.
+      This basically means that either a device features several chip
+      selects, or that different devices must be seen as a single
+      bigger chip. This basically doubles (or more) the total address
+      space with only a single additional wire, while still needing
+      to repeat the commands when crossing a chip boundary. The size of
+      each chip should be provided as members of the array.
+    $ref: /schemas/types.yaml#/definitions/uint64-array
+    minItems: 2
+    maxItems: 4
+
+  parallel-memories:
+    description: Several SPI memories can be wired in parallel mode.
+      The devices are physically on a different buses but will always
+      act synchronously as each data word is spread across the
+      different memories (eg. even bits are stored in one memory, odd
+      bits in the other). This basically doubles the address space and
+      the throughput while greatly complexifying the wiring because as
+      many busses as devices must be wired. The size of each chip should
+      be provided as members of the array.
+    $ref: /schemas/types.yaml#/definitions/uint64-array
+    minItems: 2
+    maxItems: 4
+
 # The controller specific properties go here.
 allOf:
   - $ref: cdns,qspi-nor-peripheral-props.yaml#
-- 
2.27.0

Re: [PATCH v6 2/3] spi: dt-bindings: Describe stacked/parallel memories modes

[Rob Herring]

On Wed, 26 Jan 2022 12:26:06 +0100, Miquel Raynal wrote:
> Describe two new memories modes:
> - A stacked mode when the bus is common but the address space extended
>   with an additinals wires.
> - A parallel mode with parallel busses accessing parallel flashes where
>   the data is spread.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Acked-by: Pratyush Yadav <p.yadav@ti.com>
> ---
>  .../bindings/spi/spi-peripheral-props.yaml    | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v6 3/3] spi: dt-bindings: Add an example with two stacked flashes

[Miquel Raynal]

Provide an example of how to describe two flashes in eg. stacked mode.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/spi/spi-controller.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml
index 36b72518f565..0f4d40218400 100644
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
@@ -139,4 +139,11 @@ examples:
             spi-max-frequency = <100000>;
             reg = <1>;
         };
+
+        flash@2 {
+          compatible = "jedec,spi-nor";
+          spi-max-frequency = <50000000>;
+          reg = <2>, <3>;
+          stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
+        };
     };
-- 
2.27.0

Re: [PATCH v6 0/3] Stacked/parallel memories bindings

[Michal Simek]

Hi Mark

On 1/26/22 12:26, Miquel Raynal wrote:
> Hello Rob, Mark, Tudor & Pratyush,
> 
> Here is a sixth versions for these bindings, which applies on top of
> the v5.17-rc1 now that Pratyush's work as been merged.
> (https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/)
> 
> Cheers,
> Miquèl
> 
> Changes in v6:
> * Added Pratyush's acks.
> * The tooling now validates the binding (updating dt-schema is
>    necesary).
> * Updated the maxItems field to 4 as a "big enough value" as discussed.
> 
> Changes in v5:
> * Used the uint64-array instead of the matrix type.
> * Updated the example as well to use a single "/bits/ 64" cast because
>    doing it twice, despite being supported by the language itself, is not
>    yet something that we can use for describing bindings.
> 
> Changes in v4:
> * Changed the type of properties to uint64-arrays in order to be able to
>    describe the size of each element in the array.
> * Updated the example accordingly.
> 
> Changes in v3:
> * Rebased on top of Pratyush's recent changes.
> * Dropped the commit allowing to provide two reg entries on the node
>    name.
> * Dropped the commit referencing spi-controller.yaml from
>    jedec,spi-nor.yaml, now replaced by spi-peripheral-props.yaml and
>    already done in Pratyush's series.
> * Added Rob's Ack.
> * Enhanced a commit message.
> * Moved the new properties to the new SPI peripheral binding file.
> 
> Changes in v2:
> * Dropped the dtc changes for now.
> * Moved the properties in the device's nodes, not the controller's.
> * Dropped the useless #address-cells change.
> * Added a missing "minItems".
> * Moved the new properties in the spi-controller.yaml file.
> * Added an example using two stacked memories in the
>    spi-controller.yaml file.
> * Renamed the properties to drop the Xilinx prefix.
> * Added a patch to fix the spi-nor jedec yaml file.
> 
> Miquel Raynal (3):
>    dt-bindings: mtd: spi-nor: Allow two CS per device
>    spi: dt-bindings: Describe stacked/parallel memories modes
>    spi: dt-bindings: Add an example with two stacked flashes
> 
>   .../bindings/mtd/jedec,spi-nor.yaml           |  3 ++-
>   .../bindings/spi/spi-controller.yaml          |  7 ++++++
>   .../bindings/spi/spi-peripheral-props.yaml    | 25 +++++++++++++++++++
>   3 files changed, 34 insertions(+), 1 deletion(-)
> 

Can you please pick up this series?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

Re: [PATCH v6 0/3] Stacked/parallel memories bindings

[Mark Brown]

On Wed, 26 Jan 2022 12:26:04 +0100, Miquel Raynal wrote:
> Here is a sixth versions for these bindings, which applies on top of
> the v5.17-rc1 now that Pratyush's work as been merged.
> (https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/)
> 
> Cheers,
> Miquèl
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] dt-bindings: mtd: spi-nor: Allow two CS per device
      commit: b252ada293d5d30566121c61fa7552e74396d533
[2/3] spi: dt-bindings: Describe stacked/parallel memories modes
      commit: e2edd1b64f1c79e8abda365149ed62a2a9a494b4
[3/3] spi: dt-bindings: Add an example with two stacked flashes
      commit: eba5368503b4291db7819512600fa014ea17c5a8

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark