From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03D192586D8; Mon, 10 Feb 2025 16:52:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739206344; cv=none; b=UPz1pxo+8i5K+iNBLfo+M/bdp0RcqVzBPMXDUTBMEdwKnaSrodySFDWK6ALDhw4Y/9Foso6RN0NnSGR11hfL/+NhkfbKuzpswdgyaXr7wVus70VytwcWH5w0B9mBNyusxK5reNmYXoGbcPGsO2FmKxJ9vApE801qVluEgKmrul0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739206344; c=relaxed/simple; bh=Fq0nz+qJpFshRjC9OyZc9Qy66WzrIAZthe2Fsrt5qak=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UxWrAYrjTMxqNkiSa0wI1RmuXlUSiRtKM9FLFkxyvZgwKB8c/EqRXuxVUuAE3AaAak/HGJW53jkksJHz4XHUn9bDnGnQ+OyB7yvI8KrIb7y+DNAkejR4kSTE7jf6x5AVHhIbKeXmzZKG80eg/D2QzZbkF9bSGtYQetPC0mykuwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Wnkcrlre; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wnkcrlre" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739206343; x=1770742343; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Fq0nz+qJpFshRjC9OyZc9Qy66WzrIAZthe2Fsrt5qak=; b=WnkcrlreHqfO+qwoK/P5y5xwFVVMn478zKm2SkDgQL0UqLO1JKiNA3Zo pNvAEs53fJixsY24AkWB2yIoe8SRkSoCbF9w3mMHhL9yBmtPC44/UQmLO CCnL6cFzPops7cDdFnEg0HB9WD+mEbP9JHxE5/7hoF/piLYo4jltUTIBF aZrCXKkrNDuKn0EiUD5C09fPufBlHeD+tNjJXV4zPIrxVNf4vI9HI3U4y iITad0mrxfNv/Fyah0i//V9TKFqYmk9ualoEu5CRzYXAu5Y0uTEZW8BlP 3UM6a3XeqangCjragomjU96NWKmdUFgIeUwNV/rGG92pHGpDzor7WHe+b A==; X-CSE-ConnectionGUID: nZ88tRsfRc+/WJn2YJtKBQ== X-CSE-MsgGUID: qdfmsfdsSxSsdUzSkn8WKw== X-IronPort-AV: E=McAfee;i="6700,10204,11341"; a="57334255" X-IronPort-AV: E=Sophos;i="6.13,275,1732608000"; d="scan'208";a="57334255" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2025 08:52:21 -0800 X-CSE-ConnectionGUID: tdRaJw2FRe6OqFX167lc9g== X-CSE-MsgGUID: 5tCAIJnSRUWFzFUo1rA+zQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="149431797" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 10 Feb 2025 08:52:18 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 45C362F2; Mon, 10 Feb 2025 18:52:16 +0200 (EET) Date: Mon, 10 Feb 2025 18:52:16 +0200 From: Andy Shevchenko To: David Lechner Cc: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?iso-8859-1?Q?S=E1?= , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, Jonathan Cameron Subject: Re: [PATCH v8 04/17] spi: offload-trigger: add PWM trigger driver Message-ID: References: <20250207-dlech-mainline-spi-engine-offload-2-v8-0-e48a489be48c@baylibre.com> <20250207-dlech-mainline-spi-engine-offload-2-v8-4-e48a489be48c@baylibre.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250207-dlech-mainline-spi-engine-offload-2-v8-4-e48a489be48c@baylibre.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Fri, Feb 07, 2025 at 02:09:01PM -0600, David Lechner wrote: > Add a new driver for a generic PWM trigger for SPI offloads. ... > +#include > +#include > +#include > +#include > +#include You probably want also to have (in the comments the examples of the users) device.h // dev_*(), devm_kzalloc() err.h // EINVAL, PTR_ERR(), ... math.h // DIV_ROUND_UP_ULL() module.h // MODULE_*() property.h // dev_fwnode() time.h // NSEC_PER_SEC > +struct spi_offload_trigger_pwm_state { > + struct device *dev; > + struct pwm_device *pwm; > +}; -- With Best Regards, Andy Shevchenko