From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B329C001DC for ; Mon, 17 Jul 2023 17:39:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230029AbjGQRjx (ORCPT ); Mon, 17 Jul 2023 13:39:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229861AbjGQRjx (ORCPT ); Mon, 17 Jul 2023 13:39:53 -0400 X-Greylist: delayed 1571 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 17 Jul 2023 10:39:52 PDT Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05672E3 for ; Mon, 17 Jul 2023 10:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Content-Transfer-Encoding:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=I1IBVkksfG+qQKrTGDGnSHsQlmlbsma3MfWiTgZTY6Q=; b=WgcaRL2JCPPRtYMOzHVIebs+X/ pSd/CNjzFIkV8z2rzh68t+tmKHzKfkwBTQpFpUfp7bhJHRpXzBqLbgWGYtYrxdIgN78mvXsq/NpwJ jYfAzYIIXYwgwqKquOFGD51QOX3z4bn91kzibs5kdaMePpFqRe5JyCKadAV/I4XvVSqW9Y8A8U0AE VPDhD4y7A3FAk7SPqFlpSAPtoUBiRm3ImRrPCdrkW2rKh7CKKuAD34dJURw7cJRugluO6Bz7RWcNB lf8UrLppn8TFn9NOzLxYADjzVgRKBGeATTh9qVqUilhBWsDL5urmRIXGimUYSMWovSOXGvT0p3EfW 2B4UJDMQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qLRmy-00AkKP-0S; Mon, 17 Jul 2023 19:13:36 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1qLRmw-009E8k-21; Mon, 17 Jul 2023 19:13:34 +0200 Date: Mon, 17 Jul 2023 19:13:34 +0200 From: Aurelien Jarno To: William Qiu Cc: devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu Subject: Re: [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC Message-ID: Mail-Followup-To: William Qiu , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu References: <20230704090453.83980-1-william.qiu@starfivetech.com> <20230704090453.83980-4-william.qiu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230704090453.83980-4-william.qiu@starfivetech.com> User-Agent: Mutt/2.2.9 (2022-11-12) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi, On 2023-07-04 17:04, William Qiu wrote: > Add the quad spi controller node for the StarFive JH7110 SoC. > > Co-developed-by: Ziv Xu > Signed-off-by: Ziv Xu > Signed-off-by: William Qiu > Reviewed-by: Hal Feng > --- > .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 2a6d81609284..983b683e2f27 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -126,6 +126,38 @@ &i2c6 { > status = "okay"; > }; > > +&qspi { > + #address-cells = <1>; > + #size-cells = <0>; > + > + nor_flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + cdns,read-delay = <5>; > + spi-max-frequency = <12000000>; > + cdns,tshsl-ns = <1>; > + cdns,tsd2d-ns = <1>; > + cdns,tchsh-ns = <1>; > + cdns,tslch-ns = <1>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + spl@0 { > + reg = <0x0 0x20000>; > + }; > + uboot@100000 { > + reg = <0x100000 0x300000>; > + }; > + data@f00000 { > + reg = <0xf00000 0x100000>; > + }; It appears that this uses the old layout for the SPI flash. The new layout is described there: https://doc-en.rvspace.org/VisionFive2/Boot_UG/JH7110_SDK/boot_address_allocation.html Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net