[PATCH v9 0/6] Add octal DTR support for Macronix flash

[PATCH v9 0/6] Add octal DTR support for Macronix flash

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

Add method for Macronix Octal DTR Eable/Disable.
Merge Tudor's patch "Allow specifying the byte order in DTR mode"

v9:
  Change the name of the configuration register 2 for Macronix Octal flash.
  Fix the bit value in __pad of struct spi_mem_op.
  Use the local variable proto instead of nor->read_proto.

v8:
  Supplement missing S-o-b
  Remove function spi_nor_is_octal_dtr_swab16
  Split IDs by MX25 & MX66
  Add dump of capability in debugfs
  Add dump of params in debugfs
  Add dump of reult for mtd-utils tests
  Add SNOR_ID(0xC2) in last of Macronix ID table

v7:
  Add dtr_swab16 judgement to enable/disable Macronix xSPI host
  controller swap byte feature.

v6:
  Add byte swap support for spi-mxic.c
  Remove flash name in ID table.

v5:
  Remove manufacturer read id function.
  For increased readability, separate Flash IDs based on whether
  it supports RWW feature.

v4:
  Add patch for adding manufacturer read id function.
  remove patch "hook manufacturer by checking first byte id" 

v3:
  Add patch for hook manufacturer by comparing ID 1st byte.
  Add patches for specifying the byte order in DTR mode by merging
  Tudor's patch.

v2:
  Following exsting rules to re-create Macronix specify Octal DTR method.
  change signature to jaimeliao@mxic.com.tw
  Clear sector size information in flash INFO.

AlvinZhou (6):
  mtd: spi-nor: add Octal DTR support for Macronix flash
  spi: spi-mem: Allow specifying the byte order in Octal DTR mode
  mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
  mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
  spi: mxic: Add support for swapping byte
  mtd: spi-nor: add support for Macronix Octal flash

 drivers/mtd/spi-nor/core.c     |  4 ++
 drivers/mtd/spi-nor/core.h     |  1 +
 drivers/mtd/spi-nor/macronix.c | 95 +++++++++++++++++++++++++++++++++-
 drivers/mtd/spi-nor/sfdp.c     |  4 ++
 drivers/mtd/spi-nor/sfdp.h     |  1 +
 drivers/spi/spi-mem.c          |  3 ++
 drivers/spi/spi-mxic.c         | 17 ++++--
 include/linux/spi/spi-mem.h    |  8 ++-
 8 files changed, 127 insertions(+), 6 deletions(-)

-- 
2.25.1

[PATCH v9 1/6] mtd: spi-nor: add Octal DTR support for Macronix flash

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

Create Macronix specify method for enable Octal DTR mode and
set 20 dummy cycles to allow running at the maximum supported
frequency for Macronix Octal flash.

Use number of dummy cycles which is parse by SFDP then convert
it to bit pattern and set in CR2 register.
Set CR2 register for enable octal DTR mode.

Use Read ID to confirm that enabling/diabling octal DTR mode
was successful.

Macronix ID format is A-A-B-B-C-C in octal DTR mode.
To ensure the successful enablement of octal DTR mode, confirm
that the 6-byte data is entirely correct.

Co-developed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/mtd/spi-nor/macronix.c | 91 ++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index ea6be95e75a5..f039819a5252 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -8,6 +8,24 @@
 
 #include "core.h"
 
+#define MXIC_NOR_OP_RD_CR2	0x71		/* Read configuration register 2 opcode */
+#define MXIC_NOR_OP_WR_CR2	0x72		/* Write configuration register 2 opcode */
+#define MXIC_NOR_ADDR_CR2_MODE	0x00000000	/* CR2 address for setting spi/sopi/dopi mode */
+#define MXIC_NOR_ADDR_CR2_DC	0x00000300	/* CR2 address for setting dummy cycles */
+#define MXIC_NOR_REG_DOPI_EN	0x2		/* Enable Octal DTR */
+#define MXIC_NOR_REG_SPI_EN	0x0		/* Enable SPI */
+
+/* Convert dummy cycles to bit pattern */
+#define MXIC_NOR_REG_DC(p) \
+	((20 - (p)) >> 1)
+
+/* Macronix write CR2 operations */
+#define MXIC_NOR_WR_CR2(addr, ndata, buf)			\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(MXIC_NOR_OP_WR_CR2, 0),	\
+		   SPI_MEM_OP_ADDR(4, addr, 0),			\
+		   SPI_MEM_OP_NO_DUMMY,				\
+		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+
 static int
 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
 			    const struct sfdp_parameter_header *bfpt_header,
@@ -185,6 +203,78 @@ static const struct flash_info macronix_nor_parts[] = {
 	}
 };
 
+static int macronix_nor_octal_dtr_en(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf, i;
+	int ret;
+
+	/* Use dummy cycles which is parse by SFDP and convert to bit pattern. */
+	buf[0] = MXIC_NOR_REG_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states);
+	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_DC, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	/* Set the octal and DTR enable bits. */
+	buf[0] = MXIC_NOR_REG_DOPI_EN;
+	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	/* Macronix SPI-NOR flash 8D-8D-8D read ID would get 6 bytes data A-A-B-B-C-C */
+	for (i = 0; i < nor->info->id->len; i++)
+		if (buf[i * 2] != buf[(i * 2) + 1] || buf[i * 2] != nor->info->id->bytes[i])
+			return -EINVAL;
+
+	return 0;
+}
+
+static int macronix_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/*
+	 * The register is 1-byte wide, but 1-byte transactions are not
+	 * allowed in 8D-8D-8D mode. Since there is no register at the
+	 * next location, just initialize the value to 0 and let the
+	 * transaction go on.
+	 */
+	buf[0] = MXIC_NOR_REG_SPI_EN;
+	buf[1] = 0x0;
+	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 2, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
+{
+	return enable ? macronix_nor_octal_dtr_en(nor) : macronix_nor_octal_dtr_dis(nor);
+}
+
 static void macronix_nor_default_init(struct spi_nor *nor)
 {
 	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
@@ -194,6 +284,7 @@ static int macronix_nor_late_init(struct spi_nor *nor)
 {
 	if (!nor->params->set_4byte_addr_mode)
 		nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
+	nor->params->set_octal_dtr = macronix_nor_set_octal_dtr;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v9 2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

From: Tudor Ambarus <tudor.ambarus@linaro.org>

There are NOR flashes (Macronix) that swap the bytes on a 16-bit
boundary when configured in Octal DTR mode. The byte order of
16-bit words is swapped when read or written in Octal Double
Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
Swapping the bytes may introduce some endianness problems. It can
affect the boot sequence if the entire boot sequence is not handled
in either 8D-8D-8D mode or 1-1-1 mode. Therefore, it is necessary
to swap the bytes back to ensure the same byte order as in STR modes.
Fortunately there are controllers that could swap the bytes back at
runtime, addressing the flash's endiannesses requirements. Provide a
way for the upper layers to specify the byte order in Octal DTR mode.

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/spi/spi-mem.c       | 3 +++
 include/linux/spi/spi-mem.h | 8 +++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 17b8baf749e6..abc6792e738c 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -172,6 +172,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
 		if (!spi_mem_controller_is_capable(ctlr, dtr))
 			return false;
 
+		if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16))
+			return false;
+
 		if (op->cmd.nbytes != 2)
 			return false;
 	} else {
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index f866d5c8ed32..c46d2b8029be 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -90,6 +90,8 @@ enum spi_mem_data_dir {
  * @data.buswidth: number of IO lanes used to send/receive the data
  * @data.dtr: whether the data should be sent in DTR mode or not
  * @data.ecc: whether error correction is required or not
+ * @data.swap16: whether the byte order of 16-bit words is swapped when read
+ *		 or written in Octal DTR mode compared to STR mode.
  * @data.dir: direction of the transfer
  * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  *		 operation does not involve transferring data
@@ -124,7 +126,8 @@ struct spi_mem_op {
 		u8 buswidth;
 		u8 dtr : 1;
 		u8 ecc : 1;
-		u8 __pad : 6;
+		u8 swap16 : 1;
+		u8 __pad : 5;
 		enum spi_mem_data_dir dir;
 		unsigned int nbytes;
 		union {
@@ -297,10 +300,13 @@ struct spi_controller_mem_ops {
  * struct spi_controller_mem_caps - SPI memory controller capabilities
  * @dtr: Supports DTR operations
  * @ecc: Supports operations with error correction
+ * @swap16: Supports swapping bytes on a 16 bit boundary when configured in
+ *	    Octal DTR
  */
 struct spi_controller_mem_caps {
 	bool dtr;
 	bool ecc;
+	bool swap16;
 };
 
 #define spi_mem_controller_is_capable(ctlr, cap)	\
-- 
2.25.1

Re: [PATCH v9 2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 539 bytes --]

On Thu, Jul 18, 2024 at 11:46:10AM +0800, AlvinZhou wrote:
> From: AlvinZhou <alvinzhou@mxic.com.tw>
> 
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> 
> There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> boundary when configured in Octal DTR mode. The byte order of
> 16-bit words is swapped when read or written in Octal Double
> Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses

Acked-by: Mark Brown <broonie@kernel.org>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PATCH v9 3/6] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

From: Tudor Ambarus <tudor.ambarus@linaro.org>

Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controller is not capable of swapping the bytes, the protocol is downgrade
via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the
bytes is always done regardless if it's a data or register access, so that
it comply with the JESD216 requirements: "Byte order of 16-bit words is
swapped when read in 8D-8D-8D mode compared to 1-1-1".

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/mtd/spi-nor/core.c | 4 ++++
 drivers/mtd/spi-nor/core.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 028514c6996f..31f57b17023f 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -113,6 +113,10 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
 		op->cmd.opcode = (op->cmd.opcode << 8) | ext;
 		op->cmd.nbytes = 2;
 	}
+
+	/* SWAP16 is only applicable when Octal DTR mode */
+	if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
+		op->data.swap16 = true;
 }
 
 /**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 442786685515..baf6c4b5912b 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
 	SNOR_F_RWW		= BIT(14),
 	SNOR_F_ECC		= BIT(15),
 	SNOR_F_NO_WP		= BIT(16),
+	SNOR_F_SWAP16		= BIT(17),
 };
 
 struct spi_nor_read_command {
-- 
2.25.1

[PATCH v9 4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

From: Tudor Ambarus <tudor.ambarus@linaro.org>

Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode.

This info flag will be used as a basis to determine whether
there is byte swapping of data for SPI NOR flash in octal
DTR mode.

The controller driver will check whether byte swapping is supported
to determin whether the corresponding operation are supported, thus
avoiding the generation of unexpected data order.

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/mtd/spi-nor/sfdp.c | 4 ++++
 drivers/mtd/spi-nor/sfdp.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 5b1117265bd2..21727f9a4ac6 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -671,6 +671,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 		return -EOPNOTSUPP;
 	}
 
+	/* Byte order in 8D-8D-8D mode */
+	if (bfpt.dwords[SFDP_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED)
+		nor->flags |= SNOR_F_SWAP16;
+
 	return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt);
 }
 
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index da0fe5aa9bb0..d90cbd7331f7 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -130,6 +130,7 @@ struct sfdp_bfpt {
 #define BFPT_DWORD18_CMD_EXT_INV		(0x1UL << 29) /* Invert */
 #define BFPT_DWORD18_CMD_EXT_RES		(0x2UL << 29) /* Reserved */
 #define BFPT_DWORD18_CMD_EXT_16B		(0x3UL << 29) /* 16-bit opcode */
+#define BFPT_DWORD18_BYTE_ORDER_SWAPPED		BIT(31)	/* Byte sawp of 16-bit in 8D-8D-8D mode */
 
 struct sfdp_parameter_header {
 	u8		id_lsb;
-- 
2.25.1

[PATCH v9 5/6] spi: mxic: Add support for swapping byte

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

Some SPI-NOR flash swap the bytes on a 16-bit boundary when
configured in Octal DTR mode. It means data format D0 D1 D2 D3
would be swapped to D1 D0 D3 D2. So that whether controller
support swapping bytes should be checked before enable Octal
DTR mode. Add swap byte support on a 16-bit boundary when
configured in Octal DTR mode for Macronix xSPI host controller
dirver.

According dtr_swab in operation to enable/disable Macronix
xSPI host controller swap byte feature.

To make sure swap byte feature is working well, program data in
1S-1S-1S mode then read back and compare read data in 8D-8D-8D
mode.

This feature have been validated on byte-swap flash and
non-byte-swap flash.

Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine
the byte swap feature disabled/enabled and swap byte feature is
working on 8D-8D-8D mode only.

Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/spi/spi-mxic.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 6156d691630a..f4e2f506bb2a 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
 	       mxic->regs + HC_CFG);
 }
 
-static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
+static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,
+				bool swap16)
 {
 	int nio = 1;
 
@@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
 	else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
 		nio = 2;
 
+	if (swap16)
+		flags &= ~HC_CFG_DATA_PASS;
+	else
+		flags |= HC_CFG_DATA_PASS;
+
 	return flags | HC_CFG_NIO(nio) |
 	       HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |
 	       HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1);
@@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
 	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
 		return -EINVAL;
 
-	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
+	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+	       mxic->regs + HC_CFG);
 
 	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
 	       mxic->regs + LRD_CFG);
@@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
 	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
 		return -EINVAL;
 
-	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
+	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+	       mxic->regs + HC_CFG);
 
 	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
 	       mxic->regs + LWR_CFG);
@@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
 	if (ret)
 		return ret;
 
-	writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
+	writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),
 	       mxic->regs + HC_CFG);
 
 	writel(HC_EN_BIT, mxic->regs + HC_EN);
@@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
 
 static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
 	.dtr = true,
+	.swap16 = true,
 	.ecc = true,
 };
 
-- 
2.25.1

Re: [PATCH v9 5/6] spi: mxic: Add support for swapping byte

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 556 bytes --]

On Thu, Jul 18, 2024 at 11:46:13AM +0800, AlvinZhou wrote:
> From: AlvinZhou <alvinzhou@mxic.com.tw>
> 
> Some SPI-NOR flash swap the bytes on a 16-bit boundary when
> configured in Octal DTR mode. It means data format D0 D1 D2 D3
> would be swapped to D1 D0 D3 D2. So that whether controller
> support swapping bytes should be checked before enable Octal
> DTR mode. Add swap byte support on a 16-bit boundary when
> configured in Octal DTR mode for Macronix xSPI host controller
> dirver.

driver

Acked-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v9 5/6] spi: mxic: Add support for swapping byte

[Tudor Ambarus]

Hi, Mark,

On 9/24/24 12:38 PM, Mark Brown wrote:
> On Thu, Jul 18, 2024 at 11:46:13AM +0800, AlvinZhou wrote:
>> From: AlvinZhou <alvinzhou@mxic.com.tw>
>>
>> Some SPI-NOR flash swap the bytes on a 16-bit boundary when
>> configured in Octal DTR mode. It means data format D0 D1 D2 D3
>> would be swapped to D1 D0 D3 D2. So that whether controller
>> support swapping bytes should be checked before enable Octal
>> DTR mode. Add swap byte support on a 16-bit boundary when
>> configured in Octal DTR mode for Macronix xSPI host controller
>> dirver.
> 
> driver

I can amend that.

> 
> Acked-by: Mark Brown <broonie@kernel.org>

I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches
through mtd and provide you an immutable tag? I can do that after -rc1
is out.

Or you can take them directly through spi/, but I'll need an immutable tag.

Thanks,
ta

Re: [PATCH v9 5/6] spi: mxic: Add support for swapping byte

[Mark Brown]

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On Tue, Sep 24, 2024 at 03:29:37PM +0100, Tudor Ambarus wrote:
> On 9/24/24 12:38 PM, Mark Brown wrote:

> > Acked-by: Mark Brown <broonie@kernel.org>

> I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches
> through mtd and provide you an immutable tag? I can do that after -rc1
> is out.

> Or you can take them directly through spi/, but I'll need an immutable tag.

If you apply and send me a pull request with the tag that should be
good.

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Re: [PATCH v9 5/6] spi: mxic: Add support for swapping byte

[Tudor Ambarus]

On 9/24/24 3:52 PM, Mark Brown wrote:
> On Tue, Sep 24, 2024 at 03:29:37PM +0100, Tudor Ambarus wrote:
>> On 9/24/24 12:38 PM, Mark Brown wrote:
> 
>>> Acked-by: Mark Brown <broonie@kernel.org>
> 
>> I'm fine with the SPI bits as well. Shall I take the SPI/SPIMEM patches
>> through mtd and provide you an immutable tag? I can do that after -rc1
>> is out.
> 
>> Or you can take them directly through spi/, but I'll need an immutable tag.
> 
> If you apply and send me a pull request with the tag that should be
> good.

okay, will do, after -rc1 is out.

Cheers,
ta

[PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[AlvinZhou]

From: AlvinZhou <alvinzhou@mxic.com.tw>

Adding Manufacture ID 0xC2 in last of ID table because of
Octal Flash need manufacturer fixup for enabling/disabling
Octal DTR mode.

Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
---
 drivers/mtd/spi-nor/macronix.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index f039819a5252..1a8ccebdfe0e 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
 		.name = "mx25l3255e",
 		.size = SZ_4M,
 		.no_sfdp_flags = SECT_4K,
-	}
+	},
+	/* Need the manufacturer fixups, Keep this last */
+	{ .id = SNOR_ID(0xc2) }
 };
 
 static int macronix_nor_octal_dtr_en(struct spi_nor *nor)
-- 
2.25.1

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Tudor Ambarus]

Hi, Alvin,

I quickly skimmed over the previous 5 patches and they are looking fine.

I don't get this patch however.

On 7/18/24 4:46 AM, AlvinZhou wrote:
> From: AlvinZhou <alvinzhou@mxic.com.tw>
> 
> Adding Manufacture ID 0xC2 in last of ID table because of
> Octal Flash need manufacturer fixup for enabling/disabling
> Octal DTR mode.
> 
> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
> ---
>  drivers/mtd/spi-nor/macronix.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index f039819a5252..1a8ccebdfe0e 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
>  		.name = "mx25l3255e",
>  		.size = SZ_4M,
>  		.no_sfdp_flags = SECT_4K,
> -	}
> +	},
> +	/* Need the manufacturer fixups, Keep this last */
> +	{ .id = SNOR_ID(0xc2) }
>  };
>  

Could you please elaborate why you need just the manufacturer id here? I
would have expected to see a specific flash entry instead.

Thanks,
ta

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Michael Walle]

Hi,

> > --- a/drivers/mtd/spi-nor/macronix.c
> > +++ b/drivers/mtd/spi-nor/macronix.c
> > @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
> >  		.name = "mx25l3255e",
> >  		.size = SZ_4M,
> >  		.no_sfdp_flags = SECT_4K,
> > -	}
> > +	},
> > +	/* Need the manufacturer fixups, Keep this last */
> > +	{ .id = SNOR_ID(0xc2) }
> >  };
> >  
>
> Could you please elaborate why you need just the manufacturer id here? I
> would have expected to see a specific flash entry instead.

I can't find the thread anymore as this is going on for forever, but
that was my suggestion. That's a catch all to have the manufacturer
fixup applied for any macronix flashes instead of having to list
each flash id here.

-michael

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Alvin Zhou]

Hi Tudor,

Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：
>
> Hi, Alvin,
>
> I quickly skimmed over the previous 5 patches and they are looking fine.
>
> I don't get this patch however.
>
> On 7/18/24 4:46 AM, AlvinZhou wrote:
> > From: AlvinZhou <alvinzhou@mxic.com.tw>
> >
> > Adding Manufacture ID 0xC2 in last of ID table because of
> > Octal Flash need manufacturer fixup for enabling/disabling
> > Octal DTR mode.
> >
> > Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> > Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
> > ---
> >  drivers/mtd/spi-nor/macronix.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> > index f039819a5252..1a8ccebdfe0e 100644
> > --- a/drivers/mtd/spi-nor/macronix.c
> > +++ b/drivers/mtd/spi-nor/macronix.c
> > @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
> >               .name = "mx25l3255e",
> >               .size = SZ_4M,
> >               .no_sfdp_flags = SECT_4K,
> > -     }
> > +     },
> > +     /* Need the manufacturer fixups, Keep this last */
> > +     { .id = SNOR_ID(0xc2) }
> >  };
> >
>
> Could you please elaborate why you need just the manufacturer id here? I
> would have expected to see a specific flash entry instead.

Grateful to Michael for the valuable suggestion. This addition of the
Macronix manufacturer ID enables the fixup functions such as
macronix_nor_set_octal_dtr to be executed without the need to
create separate ID entries for each Octal DTR NOR Flash in the
flash_info.

>
> Thanks,
> ta

Thanks,
Alvin

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Tudor Ambarus]

On 9/24/24 4:25 AM, Alvin Zhou wrote:
> Hi Tudor,
> 
> Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：
>>
>> Hi, Alvin,
>>
>> I quickly skimmed over the previous 5 patches and they are looking fine.
>>
>> I don't get this patch however.
>>
>> On 7/18/24 4:46 AM, AlvinZhou wrote:
>>> From: AlvinZhou <alvinzhou@mxic.com.tw>
>>>
>>> Adding Manufacture ID 0xC2 in last of ID table because of
>>> Octal Flash need manufacturer fixup for enabling/disabling
>>> Octal DTR mode.
>>>
>>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
>>> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
>>> ---
>>>  drivers/mtd/spi-nor/macronix.c | 4 +++-
>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
>>> index f039819a5252..1a8ccebdfe0e 100644
>>> --- a/drivers/mtd/spi-nor/macronix.c
>>> +++ b/drivers/mtd/spi-nor/macronix.c
>>> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
>>>               .name = "mx25l3255e",
>>>               .size = SZ_4M,
>>>               .no_sfdp_flags = SECT_4K,
>>> -     }
>>> +     },
>>> +     /* Need the manufacturer fixups, Keep this last */
>>> +     { .id = SNOR_ID(0xc2) }
>>>  };
>>>
>>
>> Could you please elaborate why you need just the manufacturer id here? I
>> would have expected to see a specific flash entry instead.
> 
> Grateful to Michael for the valuable suggestion. This addition of the
> Macronix manufacturer ID enables the fixup functions such as
> macronix_nor_set_octal_dtr to be executed without the need to
> create separate ID entries for each Octal DTR NOR Flash in the
> flash_info.
> 

Ah, nice. Okay then. I'm going to review the rest of the patches. They
look promising ;).

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Tudor Ambarus]

On 9/24/24 7:26 AM, Tudor Ambarus wrote:
> 
> 
> On 9/24/24 4:25 AM, Alvin Zhou wrote:
>> Hi Tudor,
>>
>> Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：
>>>
>>> Hi, Alvin,
>>>
>>> I quickly skimmed over the previous 5 patches and they are looking fine.
>>>
>>> I don't get this patch however.
>>>
>>> On 7/18/24 4:46 AM, AlvinZhou wrote:
>>>> From: AlvinZhou <alvinzhou@mxic.com.tw>
>>>>
>>>> Adding Manufacture ID 0xC2 in last of ID table because of
>>>> Octal Flash need manufacturer fixup for enabling/disabling
>>>> Octal DTR mode.
>>>>
>>>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
>>>> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
>>>> ---
>>>>  drivers/mtd/spi-nor/macronix.c | 4 +++-
>>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
>>>> index f039819a5252..1a8ccebdfe0e 100644
>>>> --- a/drivers/mtd/spi-nor/macronix.c
>>>> +++ b/drivers/mtd/spi-nor/macronix.c
>>>> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
>>>>               .name = "mx25l3255e",
>>>>               .size = SZ_4M,
>>>>               .no_sfdp_flags = SECT_4K,
>>>> -     }
>>>> +     },
>>>> +     /* Need the manufacturer fixups, Keep this last */
>>>> +     { .id = SNOR_ID(0xc2) }
>>>>  };
>>>>
>>>
>>> Could you please elaborate why you need just the manufacturer id here? I
>>> would have expected to see a specific flash entry instead.
>>
>> Grateful to Michael for the valuable suggestion. This addition of the
>> Macronix manufacturer ID enables the fixup functions such as
>> macronix_nor_set_octal_dtr to be executed without the need to
>> create separate ID entries for each Octal DTR NOR Flash in the
>> flash_info.
>>
> 
> Ah, nice. Okay then. I'm going to review the rest of the patches. They
> look promising ;).

ah, but then you'll always have a matched ID, so you break the generic
flash probing for macronix. Is that correct?

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Tudor Ambarus]

On 9/24/24 7:36 AM, Tudor Ambarus wrote:
> 
> 
> On 9/24/24 7:26 AM, Tudor Ambarus wrote:
>>
>>
>> On 9/24/24 4:25 AM, Alvin Zhou wrote:
>>> Hi Tudor,
>>>
>>> Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：
>>>>
>>>> Hi, Alvin,
>>>>
>>>> I quickly skimmed over the previous 5 patches and they are looking fine.
>>>>
>>>> I don't get this patch however.
>>>>
>>>> On 7/18/24 4:46 AM, AlvinZhou wrote:
>>>>> From: AlvinZhou <alvinzhou@mxic.com.tw>
>>>>>
>>>>> Adding Manufacture ID 0xC2 in last of ID table because of
>>>>> Octal Flash need manufacturer fixup for enabling/disabling
>>>>> Octal DTR mode.
>>>>>
>>>>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
>>>>> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
>>>>> ---
>>>>>  drivers/mtd/spi-nor/macronix.c | 4 +++-
>>>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
>>>>> index f039819a5252..1a8ccebdfe0e 100644
>>>>> --- a/drivers/mtd/spi-nor/macronix.c
>>>>> +++ b/drivers/mtd/spi-nor/macronix.c
>>>>> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
>>>>>               .name = "mx25l3255e",
>>>>>               .size = SZ_4M,
>>>>>               .no_sfdp_flags = SECT_4K,
>>>>> -     }
>>>>> +     },
>>>>> +     /* Need the manufacturer fixups, Keep this last */
>>>>> +     { .id = SNOR_ID(0xc2) }
>>>>>  };
>>>>>
>>>>
>>>> Could you please elaborate why you need just the manufacturer id here? I
>>>> would have expected to see a specific flash entry instead.
>>>
>>> Grateful to Michael for the valuable suggestion. This addition of the
>>> Macronix manufacturer ID enables the fixup functions such as
>>> macronix_nor_set_octal_dtr to be executed without the need to
>>> create separate ID entries for each Octal DTR NOR Flash in the
>>> flash_info.
>>>
>>
>> Ah, nice. Okay then. I'm going to review the rest of the patches. They
>> look promising ;).
> 
> ah, but then you'll always have a matched ID, so you break the generic
> flash probing for macronix. Is that correct?

Answering myself: it's fine. Generic flash probe just fills a name,
which we don't really care about.

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Miquel Raynal]

Hi Alvin,

tudor.ambarus@linaro.org wrote on Tue, 24 Sep 2024 08:17:26 +0100:

> On 9/24/24 7:36 AM, Tudor Ambarus wrote:
> > 
> > 
> > On 9/24/24 7:26 AM, Tudor Ambarus wrote:  
> >>
> >>
> >> On 9/24/24 4:25 AM, Alvin Zhou wrote:  
> >>> Hi Tudor,
> >>>
> >>> Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：  
> >>>>
> >>>> Hi, Alvin,
> >>>>
> >>>> I quickly skimmed over the previous 5 patches and they are looking fine.
> >>>>
> >>>> I don't get this patch however.
> >>>>
> >>>> On 7/18/24 4:46 AM, AlvinZhou wrote:  
> >>>>> From: AlvinZhou <alvinzhou@mxic.com.tw>
> >>>>>
> >>>>> Adding Manufacture ID 0xC2 in last of ID table because of
> >>>>> Octal Flash need manufacturer fixup for enabling/disabling
> >>>>> Octal DTR mode.
> >>>>>
> >>>>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> >>>>> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
> >>>>> ---
> >>>>>  drivers/mtd/spi-nor/macronix.c | 4 +++-
> >>>>>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> >>>>> index f039819a5252..1a8ccebdfe0e 100644
> >>>>> --- a/drivers/mtd/spi-nor/macronix.c
> >>>>> +++ b/drivers/mtd/spi-nor/macronix.c
> >>>>> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
> >>>>>               .name = "mx25l3255e",
> >>>>>               .size = SZ_4M,
> >>>>>               .no_sfdp_flags = SECT_4K,
> >>>>> -     }
> >>>>> +     },
> >>>>> +     /* Need the manufacturer fixups, Keep this last */
> >>>>> +     { .id = SNOR_ID(0xc2) }
> >>>>>  };
> >>>>>  
> >>>>
> >>>> Could you please elaborate why you need just the manufacturer id here? I
> >>>> would have expected to see a specific flash entry instead.  
> >>>
> >>> Grateful to Michael for the valuable suggestion. This addition of the
> >>> Macronix manufacturer ID enables the fixup functions such as
> >>> macronix_nor_set_octal_dtr to be executed without the need to
> >>> create separate ID entries for each Octal DTR NOR Flash in the
> >>> flash_info.
> >>>  
> >>
> >> Ah, nice. Okay then. I'm going to review the rest of the patches. They
> >> look promising ;).  
> > 
> > ah, but then you'll always have a matched ID, so you break the generic
> > flash probing for macronix. Is that correct?  
> 
> Answering myself: it's fine. Generic flash probe just fills a name,
> which we don't really care about.

I was also a bit surprised by the diff, would you mind filling a more
complete with details on the actual goal of this entry (having all
Macronix flashes to get the fixups, without creating separate ID
entries for each of the flashes)

Thanks,
Miquèl

Re: [PATCH v9 6/6] mtd: spi-nor: add support for Macronix Octal flash

[Alvin Zhou]

Hi Miquel,

Miquel Raynal <miquel.raynal@bootlin.com> 於 2024年9月25日 週三 下午5:57寫道：
>
> Hi Alvin,
>
> tudor.ambarus@linaro.org wrote on Tue, 24 Sep 2024 08:17:26 +0100:
>
> > On 9/24/24 7:36 AM, Tudor Ambarus wrote:
> > >
> > >
> > > On 9/24/24 7:26 AM, Tudor Ambarus wrote:
> > >>
> > >>
> > >> On 9/24/24 4:25 AM, Alvin Zhou wrote:
> > >>> Hi Tudor,
> > >>>
> > >>> Tudor Ambarus <tudor.ambarus@linaro.org> 於 2024年9月23日 週一 下午2:54寫道：
> > >>>>
> > >>>> Hi, Alvin,
> > >>>>
> > >>>> I quickly skimmed over the previous 5 patches and they are looking fine.
> > >>>>
> > >>>> I don't get this patch however.
> > >>>>
> > >>>> On 7/18/24 4:46 AM, AlvinZhou wrote:
> > >>>>> From: AlvinZhou <alvinzhou@mxic.com.tw>
> > >>>>>
> > >>>>> Adding Manufacture ID 0xC2 in last of ID table because of
> > >>>>> Octal Flash need manufacturer fixup for enabling/disabling
> > >>>>> Octal DTR mode.
> > >>>>>
> > >>>>> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> > >>>>> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
> > >>>>> ---
> > >>>>>  drivers/mtd/spi-nor/macronix.c | 4 +++-
> > >>>>>  1 file changed, 3 insertions(+), 1 deletion(-)
> > >>>>>
> > >>>>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> > >>>>> index f039819a5252..1a8ccebdfe0e 100644
> > >>>>> --- a/drivers/mtd/spi-nor/macronix.c
> > >>>>> +++ b/drivers/mtd/spi-nor/macronix.c
> > >>>>> @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = {
> > >>>>>               .name = "mx25l3255e",
> > >>>>>               .size = SZ_4M,
> > >>>>>               .no_sfdp_flags = SECT_4K,
> > >>>>> -     }
> > >>>>> +     },
> > >>>>> +     /* Need the manufacturer fixups, Keep this last */
> > >>>>> +     { .id = SNOR_ID(0xc2) }
> > >>>>>  };
> > >>>>>
> > >>>>
> > >>>> Could you please elaborate why you need just the manufacturer id here? I
> > >>>> would have expected to see a specific flash entry instead.
> > >>>
> > >>> Grateful to Michael for the valuable suggestion. This addition of the
> > >>> Macronix manufacturer ID enables the fixup functions such as
> > >>> macronix_nor_set_octal_dtr to be executed without the need to
> > >>> create separate ID entries for each Octal DTR NOR Flash in the
> > >>> flash_info.
> > >>>
> > >>
> > >> Ah, nice. Okay then. I'm going to review the rest of the patches. They
> > >> look promising ;).
> > >
> > > ah, but then you'll always have a matched ID, so you break the generic
> > > flash probing for macronix. Is that correct?
> >
> > Answering myself: it's fine. Generic flash probe just fills a name,
> > which we don't really care about.
>
> I was also a bit surprised by the diff, would you mind filling a more
> complete with details on the actual goal of this entry (having all
> Macronix flashes to get the fixups, without creating separate ID
> entries for each of the flashes)

Thank you for the reminder, I will incorporate more detailed
explanations.

>
> Thanks,
> Miquèl

Thanks,
Alvin