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drivers/spi/spi-amlogic-spisg.c 716 static int aml_spisg_probe(struct platform_device *pdev) 717 { 718 struct spi_controller *ctlr; 719 struct spisg_device *spisg; 720 struct device *dev = &pdev->dev; 721 void __iomem *base; 722 int ret, irq; 723 724 const struct regmap_config aml_regmap_config = { 725 .reg_bits = 32, 726 .val_bits = 32, 727 .reg_stride = 4, 728 .max_register = SPISG_MAX_REG, 729 }; 730 731 if (of_property_read_bool(dev->of_node, "spi-slave")) 732 ctlr = spi_alloc_target(dev, sizeof(*spisg)); 733 else 734 ctlr = spi_alloc_host(dev, sizeof(*spisg)); 735 if (!ctlr) 736 return dev_err_probe(dev, -ENOMEM, "controller allocation failed\n"); 737 738 spisg = spi_controller_get_devdata(ctlr); 739 spisg->controller = ctlr; 740 741 spisg->pdev = pdev; 742 platform_set_drvdata(pdev, spisg); 743 744 base = devm_platform_ioremap_resource(pdev, 0); 745 if (IS_ERR(base)) 746 return dev_err_probe(dev, PTR_ERR(base), "resource ioremap failed\n"); This should be goto out_controller 747 748 spisg->map = devm_regmap_init_mmio(dev, base, &aml_regmap_config); 749 if (IS_ERR(spisg->map)) 750 return dev_err_probe(dev, PTR_ERR(spisg->map), "regmap init failed\n"); 751 752 irq = platform_get_irq(pdev, 0); 753 if (irq < 0) { 754 ret = irq; 755 goto out_controller; 756 } 757 758 ret = device_reset_optional(dev); 759 if (ret) 760 return dev_err_probe(dev, ret, "reset dev failed\n"); Same 761 762 ret = aml_spisg_clk_init(spisg, base); 763 if (ret) --> 764 return dev_err_probe(dev, ret, "clock init failed\n"); Same. 765 766 spisg->cfg_spi = 0; 767 spisg->cfg_start = 0; 768 spisg->cfg_bus = 0; 769 770 spisg->cfg_spi = FIELD_PREP(CFG_SFLASH_WP, 1) | 771 FIELD_PREP(CFG_SFLASH_HD, 1); 772 if (spi_controller_is_target(ctlr)) { 773 spisg->cfg_spi |= FIELD_PREP(CFG_SLAVE_EN, 1); 774 spisg->cfg_bus = FIELD_PREP(CFG_TX_TUNING, 0xf); 775 } 776 /* default pending */ 777 spisg->cfg_start = FIELD_PREP(CFG_PEND, 1); 778 779 pm_runtime_set_active(&spisg->pdev->dev); 780 pm_runtime_enable(&spisg->pdev->dev); 781 pm_runtime_resume_and_get(&spisg->pdev->dev); 782 783 ctlr->num_chipselect = 4; 784 ctlr->dev.of_node = pdev->dev.of_node; 785 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | 786 SPI_3WIRE | SPI_TX_QUAD | SPI_RX_QUAD; 787 ctlr->max_speed_hz = 1000 * 1000 * 100; 788 ctlr->min_speed_hz = 1000 * 10; 789 ctlr->setup = aml_spisg_setup; 790 ctlr->cleanup = aml_spisg_cleanup; 791 ctlr->prepare_message = aml_spisg_prepare_message; 792 ctlr->transfer_one_message = aml_spisg_transfer_one_message; 793 ctlr->target_abort = aml_spisg_target_abort; 794 ctlr->can_dma = aml_spisg_can_dma; 795 ctlr->max_dma_len = SPISG_BLOCK_MAX; 796 ctlr->auto_runtime_pm = true; 797 798 dma_set_max_seg_size(&pdev->dev, SPISG_BLOCK_MAX); 799 800 ret = devm_request_irq(&pdev->dev, irq, aml_spisg_irq, 0, NULL, spisg); 801 if (ret) { 802 dev_err(&pdev->dev, "irq request failed\n"); 803 goto out_clk; 804 } 805 806 ret = devm_spi_register_controller(dev, ctlr); 807 if (ret) { 808 dev_err(&pdev->dev, "spi controller registration failed\n"); 809 goto out_clk; 810 } 811 812 init_completion(&spisg->completion); 813 814 pm_runtime_put(&spisg->pdev->dev); 815 816 return 0; 817 out_clk: 818 if (spisg->core) 819 clk_disable_unprepare(spisg->core); 820 clk_disable_unprepare(spisg->pclk); 821 out_controller: 822 spi_controller_put(ctlr); 823 824 return ret; 825 } regards, dan carpenter