Re: [PATCH v4 4/9] spi: add multi_lane_mode field to struct spi_transfer

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Fri, Dec 19, 2025 at 03:32:12PM -0600, David Lechner wrote:
> Add a new multi_lane_mode field to struct spi_transfer to allow
> peripherals that support multiple SPI lanes to be used with a single
> SPI controller.
> 
> This requires both the peripheral and the controller to have multiple
> serializers connected to separate data lanes. It could also be used with
> a single controller and multiple peripherals that are functioning as a
> single logical device (similar to parallel memories).

...

>  	unsigned	cs_change:1;
>  	unsigned	tx_nbits:4;
>  	unsigned	rx_nbits:4;
> +
> +#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */
> +#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */
> +#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */
> +	unsigned	multi_lane_mode: 2;
> +
>  	unsigned	timestamped:1;

Btw, have you checked the layout of these bitfields? Are they all in one 32-bit
word or split? Dunno if `pahole` handles them, never actually paid attention
before.

-- 
With Best Regards,
Andy Shevchenko