From: Breno Leitao <leitao@debian.org>
To: Vishwaroop A <va@nvidia.com>
Cc: Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Mark Brown <broonie@kernel.org>,
Laxman Dewangan <ldewangan@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
Suresh Mangipudi <smangipudi@nvidia.com>,
Krishna Yarlagadda <kyarlagadda@nvidia.com>,
linux-tegra@vger.kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue
Date: Thu, 21 May 2026 08:04:08 -0700 [thread overview]
Message-ID: <ag8dgimI3SfTo1Uy@gmail.com> (raw)
In-Reply-To: <20260520192210.70216-1-va@nvidia.com>
Hello Vishwaroop,
On Wed, May 20, 2026 at 07:22:10PM +0000, Vishwaroop A wrote:
> On Wed, May 20, 2026 at 08:25:23AM -0700, Breno Leitao wrote:
> > > + status = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS);
> > > + if (!(status & QSPI_RDY))
> > > + return IRQ_NONE;
> > > +
> > > + spin_lock(&tqspi->lock);
> >
> > Can you help me to understand what the tqspi->lock protects? I am still
> > a bit confused by this lock, but at the first glance, I am wondering if
> > you don't need to have the lock while reading the status.
>
> The lock itself protects the software state that is shared between
> the ISR, the workqueue bottom-half, and the timeout handler running
> in the transfer thread.
Thanks for the reply!
I got the impression that tqspi->lock is also serializing hardware
accesses — the hard IRQ holds it across the readl(QSPI_FIFO_STATUS) and
across tegra_qspi_mask_clear_irq(), which does an RMW on QSPI_INTR_MASK
and a W1C on QSPI_TRANS_STATUS; the setup, start, error and bottom-half
paths similarly hold it across MMIO.
If the lock is really only guarding curr_xfer / status_reg / tx_status
/ rx_status, why hold it across those register accesses at all?
Thanks,
--breno
next prev parent reply other threads:[~2026-05-21 15:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 15:51 [PATCH v2 0/3] spi: tegra210-quad: Improve interrupt handling for loaded systems Vishwaroop A
2026-05-19 15:51 ` [PATCH v2 1/3] spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue Vishwaroop A
2026-05-20 9:22 ` Jon Hunter
2026-05-20 15:28 ` Mark Brown
2026-05-20 15:25 ` Breno Leitao
2026-05-20 19:22 ` Vishwaroop A
2026-05-21 15:04 ` Breno Leitao [this message]
2026-05-22 9:09 ` Vishwaroop A
2026-05-19 15:51 ` [PATCH v2 2/3] spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler Vishwaroop A
2026-05-20 9:29 ` Jon Hunter
2026-05-19 15:51 ` [PATCH v2 3/3] spi: tegra210-quad: Process small PIO transfers in hard IRQ context Vishwaroop A
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