Re: [PATCH 1/6] spi: support simultaneous assertion of multiple CS

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Tue, Jul 14, 2026 at 02:55:48AM -0300, Jonathan Santos wrote:
> Some SPI controllers allow multiple CS lines to be toggled at the same
> time. The existing code always used CS index 0 when tracking the last
> active CS in spi_set_cs(),

> and unconditionally set cs_index_mask to BIT(0) when parsing DT,

What about other cases (board info, ACPI and ancillary)?

So, the board info in case we need it, should be modified to take an array of
CSs. The ancillary seems by design a single-CS stuff, not sure if we ever would
need multi-CS. And for ACPI it is a gray area since the CS is 64-bit integer
there and theoretically we may interpret some higher bytes as amount of CS or
so, but this has to be specified.

TL;DR: Please, add a summary like the above to the commit message to explain
why those were not taken into account.

> both forcing the single CS usage.

> Modify spi_set_cs() to iterate last_cs[] using each logical CS index
> instead of always reading index 0. Modify of_spi_parse_dt() to build
> cs_index_mask from all parsed CS entries rather than hardcoding BIT(0),
> so the controller correctly identifies which CS lines belong to a device
> when asserting them simultaneously.

-- 
With Best Regards,
Andy Shevchenko