From: Dhruva Gole <d-gole@ti.com>
To: Yoshitaka Ikeda <ikeda@nskint.co.jp>
Cc: "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Vaishnav Achath <vaishnav.a@ti.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Takahiro.Kuwano@infineon.com" <Takahiro.Kuwano@infineon.com>,
Pratyush Yadav <ptyadav@amazon.de>,
Mark Brown <broonie@kernel.org>
Subject: RE: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads
Date: Thu, 27 Apr 2023 18:55:44 +0530 [thread overview]
Message-ID: <b1d30948-ba3d-a4cc-e1ed-851a9dedba7c@ti.com> (raw)
In-Reply-To: <OSZPR01MB7004D229048A950C93B40CC88B6A9@OSZPR01MB7004.jpnprd01.prod.outlook.com>
Hi,
On 27/04/23 06:11, Yoshitaka Ikeda wrote:
> Hi Dhruva,
>
>> Please can you send me the register fields information for the CQSPI
>> controller used in this device?
>> I wanted to verify if atall there were any mismatch between the controller I
>> have tested with vs your SOC's controller.
>
> You can find it in the pdf that can be obtained by pressing the download button in the upper right corner of the following website.
> - https://www.intel.com/content/www/us/en/docs/programmable/683126/15-0/introduction.html
Thanks for sharing, I went through and couldn't really find any major
changes at the controller level.
So I am wondering if some specific sequence of flash operations on your
device is exposing some issues in the driver's STIG reads.
Please can you share some logs with the following patch:
I am trying to see a pattern that may be causing issues.
I am unable to reproduce this on my end at the moment.
...
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index 6ddb2dfc0f00..5fa71dbd37ef 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1390,6 +1390,14 @@ static int cqspi_exec_mem_op(struct spi_mem *mem,
const struct spi_mem_op *op)
int ret;
ret = cqspi_mem_process(mem, op);
+ /* debug */
+ printk("**********spi_mem_op dump**************");
+ printk("addr: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, val
0x%llX", op->addr.nbytes, op->addr.buswidth, op->addr.dtr, op->addr.val);
+ printk("cmd: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, opcode
0x%X", op->cmd.nbytes, op->cmd.buswidth, op->cmd.dtr, op->cmd.opcode);
+ printk("data: nbytes:0x%X , buswidth 0x%X, dtr 0x%X, data dir
0x%X", op->data.nbytes, op->data.buswidth, op->data.dtr, op->data.dir);
+
+ printk("***************************************");
+ /* ---------------------------- */
if (ret)
dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
...
--
Thanks and Regards,
Dhruva Gole
next prev parent reply other threads:[~2023-04-27 13:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 8:10 [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 1/4] spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion Dhruva Gole
2023-01-27 15:16 ` Pratyush Yadav
2023-02-07 13:06 ` Gole, Dhruva
2023-01-25 8:10 ` [PATCH v2 2/4] spi: cadence-quadspi: Add flag for direct mode writes Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 3/4] spi: cadence-quadspi: setup ADDR Bits in cmd reads Dhruva Gole
2023-01-25 8:10 ` [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads Dhruva Gole
2023-04-26 2:34 ` Yoshitaka Ikeda
2023-04-26 7:39 ` Dhruva Gole
2023-04-27 0:41 ` Yoshitaka Ikeda
2023-04-27 13:25 ` Dhruva Gole [this message]
2023-05-08 0:36 ` Yoshitaka Ikeda
2023-05-08 5:29 ` Dhruva Gole
2023-05-08 7:44 ` Yoshitaka Ikeda
2023-05-30 2:56 ` Yoshitaka Ikeda
2023-02-14 21:10 ` [PATCH v2 0/4] STIG Mode Fixes for spi-cadence-qspi driver Mark Brown
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